Occasional Contributor
Occasional ContributorHey Stefano,
When you compile using an FPGA family (such as "Cyclone10GX"), the compiler enters an HLS flow: it only generates an IP that you need to manually integrate into your own RTL pipeline.
The fpga binary that you obtained is not executable: it is only produced for you to inspect the performance of the IP after quartus compiled it (fmax, resource usage, etc.)
Here is a code sample demonstrating how one can integrate an HLS IP into an RTL pipeline to be able to run such IP on an FPGA: https://github.com/oneapi-src/oneAPI-samples/tree/master/DirectProgramming/C%2B%2BSYCL_FPGA/Tutorials/Tools/platform_designer
You were expecting the compiler to produce a binary that could be directly executed on the FPGA: to do so, the compiler needs to understand the interface between the IP and your FPGA. This is what we call the "BSP".
Some FPGA board vendors do provide BSPs with their FPGA boards, which would have allowed you to compile your program using "icpx ... -Xstarget=<path to your BSP> ..." rather than "-Xstarget=Cyclone10GX".
In that case, and in that case only, the FPGA binary produced could have been run on the FPGA natively.
You can have a look at this documentation page to better understand the difference between the "FPGA acceleration flow" and the "HLS flow": https://www.intel.com/content/www/us/en/docs/oneapi-fpga-add-on/developer-guide/2024-0/intel-oneapi-fpga-development-flow.html
Occasional Contributor@yuguen that really clarified everything, thanks!
In the document you pointed:
something is unclear to me, you create a project in Quartus but it seems you do not create a Top-level entity, since when I do "Start Analysis and Elaboration" I get an error about that, I wonder if a top-level entity should be created anyway and what should look like. In one screenshot from the previous github I see that the top level entity is named "add" when you create the project, but then nothing is mentioned about it (what should just contain?)
Occasional ContributorHey @StefanoC
This sample demonstrates how to integrate a generated IP into an existing RTL pipeline.
In this case, the existing RTL files are located in https://github.com/oneapi-src/oneAPI-samples/blob/master/DirectProgramming/C%2B%2BSYCL_FPGA/Tutorials/Tools/platform_designer/add-quartus-sln
The "add" top level entity is found in the add.sv file.
"Step 2." tells you to copy this "add.sv" file into your Quartus project folder:
cp add-quartus-sln/add.sv add-quartus
Then, to add it to your Quartus project (step 2.v):
Following these steps (with all the other steps), Quartus should be able to understand that the "add" top level module is in this file.
Occasional ContributorThanks @yuguen for clarifying the content of add.sv
However I had followed the instructions and after I issue "make report" the following files are generated (there is no add.sv but rather add_report_di.sv which internally has a different module name and subsequently Quartus complains about missing top node. Why do I get add_report_di.sv rather than add.sv?
-rw-rw-r-- 1 tetto tetto 527 Feb 19 17:08 sys_description.txt -rw-rw-r-- 1 tetto tetto 3831 Feb 19 17:08 sys_description.legend.txt -rw-rw-r-- 1 tetto tetto 1860 Feb 19 17:08 sys_description.hex -rw-rw-r-- 1 tetto tetto 105 Feb 19 17:08 opencl.ipx -rw-rw-r-- 1 tetto tetto 4758 Feb 19 17:08 kernel_system.v -rw-rw-r-- 1 tetto tetto 3388 Feb 19 17:08 kernel_system.tcl -rw-rw-r-- 1 tetto tetto 7882 Feb 19 17:08 kernel_system.qip -rw-rw-r-- 1 tetto tetto 31 Feb 19 17:08 kernel_system_import.tcl -rw-rw-r-- 1 tetto tetto 70 Feb 19 17:08 kernel_report.tcl -rw-rw-r-- 1 tetto tetto 1197 Feb 19 17:08 ipinterfaces.xml -rw-rw-r-- 1 tetto tetto 72 Feb 19 17:08 ip_include.tcl -rw-rw-r-- 1 tetto tetto 28 Feb 19 17:08 compiler_metrics.out -rw-rw-r-- 1 tetto tetto 1197 Feb 19 17:08 board_spec.xml -rw-rw-r-- 1 tetto tetto 0 Feb 19 17:08 add_report.v -rw-rw-r-- 1 tetto tetto 3759 Feb 19 17:08 add_report_sys.v -rw-rw-r-- 1 tetto tetto 18924 Feb 19 17:08 add_report_sys_hw.tcl -rw-rw-r-- 1 tetto tetto 231 Feb 19 17:08 add_report.log -rw-rw-r-- 1 tetto tetto 19180 Feb 19 17:08 add_report_di.sv -rw-rw-r-- 1 tetto tetto 1307 Feb 19 17:08 add_report_di_inst.v -rw-rw-r-- 1 tetto tetto 17892 Feb 19 17:08 add_report_di_hw.tcl -rw-rw-r-- 1 tetto tetto 8393 Feb 19 17:08 add_report.bc.xml drwxrwxr-x 2 tetto tetto 4096 Feb 19 17:08 ip drwxrwxr-x 3 tetto tetto 4096 Feb 19 17:08 reports drwxrwxr-x 3 tetto tetto 4096 Feb 19 17:08 kernel_hdl drwxrwxr-x 3 tetto tetto 4096 Feb 19 17:08 include drwxrwxr-x 3 tetto tetto 4096 Feb 19 17:08 linux64
Also in the instruction it is sad to copy these:
cp add-quartus-sln/add.sv add-quartus $> cp add-quartus-sln/jtag.sdc add-quartus
but after "make report" the folder add-quartus-sln is not there, so also miss jtag.sdc
Occasional ContributorHey @StefanoC,
When doing "make report", you are generating RTL for the SYCL code that is in the add-oneapi folder.
This RTL top module can indeed be found in "add_report_di.sv".
This is the IP that you need to integrate into an existing RTL pipeline.
The "add_quartus_sln" folder already contains RTL, and is there to mimic your own RTL pipeline. So the "add.sv" file is already there, before you do "make report" as this is not a generated file, this is the existing RTL pipeline. You can peak into this file and see it is making a led turn on on the FPGA based on another signal. This is not possible to express using SYCL.
This tutorial shows how to connect the generated RTL from SYCL (the add_report_di.sv IP) with the existing "add.sv" RTL pipeline.
So "add" from add.sv is the top level module, that depends on the SYCL generated RTL.
The steps in the README tells you to:
1/ generate the SYCL IP
Create a Quartus project with the existing RTL files:
This also sets the top level module to "add" which is contained in the add.sv that was just copied from add-quartus-sln
Then, import the SYCL generated IP:
Then connects the two in the following steps, etc.
