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Denisa's avatar
Denisa
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1 year ago

oneAPI Board Support Package for Agilex 7 M-Series FPGA

Hello,

I have recently purchased an Intel Agilex 7 M-series FPGA for a university research project the Embedded Systems Lab (EPFL, Switzerland) and I am seeking technical support to program with it oneAPI DPC++/C++.

I don't have any experience building a Board Support Package (BSP). Is there a recipe or prebuild BSP for this FPGA to program it with oneAPI? Upon receiving the board, I performed basic tests using the Board Test System (BTS) to verify its overall functionality. However, I am unable to use some of the more advanced features of the board, which are the primary reasons for our purchase. Any help on how to use HBM2e and CXL capabilities with the oneAPI workflow would be much appreciated.

Thanks!

Denisa

10 Replies

    • Denisa's avatar
      Denisa
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      Dear Whitepeau,

      Thank you for the resource, unfortunately, these BSPs are for the Agilex 7 I-Series and F-Series Dev Kits. I have an Agilex 7 M-Series Development Kit - HBM2e Edition (3x F-Tile & 1x R-Tile): https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agm039.html. Concretely, I purchased the one from Mouser.

      Would any of these BSPs give me support to use all the resources of my Agilex 7 M-Series? If not, who can help me generate a BSP for this FPGA?

      Regards,

      Denisa

      • whitepau_altera's avatar
        whitepau_altera
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        Hello Denisa,

        I am afraid that there is no BSP for the kit you have, I expect we chose not to build a BSP for it because it has no PCIe connector (although the product page mentions PCIe connectivity is possible with an expansion board). oneAPI FPGA acceleration assumes a PCIe card (e.g. on of the devkits listed on our landing page, or a partner board listed in this document on our landing page).

        Instead of building a full oneAPI BSP, you can also use the oneAPI DPC++/C++ compiler to create IP that you can integrate using a platform designer system. We demonstrate this in the Platform Designer code sample, and the Nios V reference design. You can learn more about IP interface customization by studying the HLS Flow Interfaces code samples as well.

        Manually integrating your IP with Platform Designer (or SystemVerilog/VHDL if you are so inclined) gives you the ability to accelerate the embedded HPS, so you are not tied to an x86-64 host CPU.

        Did you engage with an Intel/Altera salesperson to get that board? If you are interested in accelerating an x86-64 host system, you should reach out to them and see if they can help you get ahold of a partner board so you can avoid building a BSP and manually integrating a system.

  • Hi Denisa,

    thanks for the reply.

    If your final deployment will be managed by a Nios® V softcore processor or even ARM Hardened processor system (HPS), then I would not recommend you to try and build a custom BSP, as that is its own complicated deployment flow (If I haven't dissuaded you, there is further documentation available in our OFS user guide)

    The board user guide suggests the following cable for PCIe connection:

    Amphenol Part Number HMC74-0631

    @BoonBengT_Altera do you have any recommendations for connecting the Agilex 7 M-Series Development Kit - HBM2e Edition (3x F-Tile & 1x R-Tile) to a PCIe slot on a host PC?

    • Denisa's avatar
      Denisa
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      Hello,

      Thank you for your replies. Do you think that the setup I envision is impossible? Should I consider returning the board or asking for a replacement with an Agilex I series dev kit? The setup will be used in research, and we will spend most of the time doing prototyping of many different HPC kernels that will stream compute at the max data transfer rate we can get (up to 1TB/s). The final deployment on a standalone FPGA board only serves as a demonstrator for an energy efficient solution that does not require keeping a server like host idle most of the time.

      It is important for to have a PCIe connection setup for prototyping and validating the FPGA accelerators with a host execution and to having an oneAPI BSP seems (at least in theory) the way to approach this.

      Assuming this is not a dead end:


      Thank you,

      Denisa

  • Porting a BSP can be tricky, but is not impossible.

    If your goal is to build PCIe-based offload accelerators for x86 hosts, then I recommend you choose a card that includes a board support package (BSP), as designing and testing a BSP can be time-consuming and is, admittedly, not very well documented.

    If you want the quickest setup time, I recommend choosing a partner board as these include vendor-supplied BSPs already: https://cdrdv2.intel.com/v1/dl/getContent/824530

    Note: from that list, only the Bittware IA-840f and IA-780i cards will be supported in the upcoming 2025.0 release of oneAPI, as the other BSPs depend on versions of Quartus® Prime that will be unsupported by oneAPI 2025.0.

    If you want to modify the BSP yourself, you may choose one of the developer kits listed on our homepage, but I do not believe those BSPs are very well tested. Unless you are comfortable debugging a BSP yourself, I suggest you choose one of the Bittware cards I mentioned above.

  • Hi @Denisa,


    Greetings, do let us know if there is any further doubts in regards to this matter that we can help with.

    Hope clarity has been provided.


    Best Wishes

    BB


  • Hi @Denisa,


    Greetings, as we do not receive any further clarification/updates on the matter, hence would assume challenge are overcome. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. For new queries, please feel free to open a new thread and we will be right with you. Pleasure having you here.


    Best Wishes

    BB