Forum Discussion
Hi @Denisa,
I believe you have managed to found the clarification on PCie5 cable and adapters support in a separate post with your relevant support specialist. (https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/MCIO-to-PCIe-Host-Adapter-for-Agilex-7-M-series-Dev-Kit/m-p/1634702#M28126)
Please do let us know if there is further clarification on regards to this post.
Hope your doubts has been clarify.
Best Wishes
BB
- Denisa1 year ago
New Contributor
Hello,
Thank you for your replies. Do you think that the setup I envision is impossible? Should I consider returning the board or asking for a replacement with an Agilex I series dev kit? The setup will be used in research, and we will spend most of the time doing prototyping of many different HPC kernels that will stream compute at the max data transfer rate we can get (up to 1TB/s). The final deployment on a standalone FPGA board only serves as a demonstrator for an energy efficient solution that does not require keeping a server like host idle most of the time.
It is important for to have a PCIe connection setup for prototyping and validating the FPGA accelerators with a host execution and to having an oneAPI BSP seems (at least in theory) the way to approach this.
Assuming this is not a dead end:
- I will have a look at the OSF guide for the Agilex 7 I series del kit, as it seems the most similar standalone fpga to the Agilex 7 M series.
- I will still need advice about how to connect FPGA to the host though PCIe. Regarding the thread about the MCIO cables (https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/MCIO-to-PCIe-Host-Adapter-for-Agilex-7-M-series-Dev-Kit/m-p/1634702#M28126), it only answered half of the question, about the MCIO Amphenol cable P/N: HMC74-1492, that are likely to work with the Agilex 7 M-series for PCIe5 because it was tested with an I-series. Do you have any suggestion for the adapter MCIO-PCIe adapter?
Thank you,Denisa