How to maping add and multiplication calculation to FPGA logic element, not DSP unit in AOC environment !In my project(most are added and multiplication calculation ) , the DSP unit used is more than 100%, but the logic element only 24% used . when the DSP is about 100%, it appear error while compile the AOCX file. So i want FPGA logic do the part of the calculation, not all by DSP???Any compile guide or document for this ??Thanks in advance !

Newer versions of the compiler will automatically map integer operations to logic when DSP overutilization is detected by the compiler. However, as far as I know, this will never happen with floating-point operations. I am pretty sure I opened a ticket with Intel Premiere Support a long time ago (before Intel acquired Altera) requesting a new feature to be added to the compiler to give programmers control over which math operations are mapped to DSPs and which are mapped to logic but as you can see, such functionality is still not available. Hence, I am afraid there is no straightforward way to fix your problem.

Hi Jinfu, As I understand it, you have some inquiries related to implementing some of your add and multiplication function in FPGA logic instead of hard DSP block. Just wonder if you are coding the function using Verilog HDL or if you are using any specific IP? Also just would like to check with you which device and Quartus version that you are using? Take CV device as example, the following are ways that you can try to see if it helps: 1. If you are using IP, for your information, you may try with LPM_MULT and then select "Use logic elements" for implementation 2. If you are using your own Verilog HDL, you can try to specific "multstyle = dsp/logic" attribute to choose between soft logic or DSP block. You may refer to Insert Template -> Verilog HDL -> Synthesis Attributes -> multstyle Attribute for further details. Please let me know if there is any concern. Thank you. Best regards, Chee Pin

HRZ: Thanks for your reply!my aocl environment is :AOCL VERSION: aocl 19.1.0.240 (Intel(R) FPGA SDK for OpenCL(TM), Version 19.1.0 Build 240 Pro Edition, Copyright (C) 2019 Intel Corporation)data type : uchar (8 bit)

hi cpchan thanks for your help!my coding is opencl, the kernel is *.cl file , not verilog HDL or any IP, the aocl compiler translate to DSP or logic by itself ! maybe any "compiler command" can help to do this when DSP over-utilization in theory , but i don't know the "compiler command"

Hi Jinfu, Thanks for your update. Sorry as I am not sure if there is any similar setting for OpenCL. Just my thought, one of the workaround that you can try is to create a logic lock for a specific module to an area without DSP block to see if it helps If this does not work, would you mind to help duplicating a new Forum case and for the OpenCL inquiry and let me konw the case number? I will help to route to our OpenCL team for further assistance. Please let me know if there is any concern. Thank you. Best regards, Chee Pin

How to maping add and multiplication calculation to FPGA logic element, not DSP unit in AOC environment

13 Replies

HRZ
Frequent Contributor
6 years ago
Newer versions of the compiler will automatically map integer operations to logic when DSP overutilization is detected by the compiler. However, as far as I know, this will never happen with floating-point operations. I am pretty sure I opened a ticket with Intel Premiere Support a long time ago (before Intel acquired Altera) requesting a new feature to be added to the compiler to give programmers control over which math operations are mapped to DSPs and which are mapped to logic but as you can see, such functionality is still not available. Hence, I am afraid there is no straightforward way to fix your problem.
- zjinf
  Occasional Contributor
  6 years ago
  HRZ:
  Thanks for your reply!
  my aocl environment is :
  AOCL VERSION: aocl 19.1.0.240 (Intel(R) FPGA SDK for OpenCL(TM), Version 19.1.0 Build 240 Pro Edition, Copyright (C) 2019 Intel Corporation)
  data type : uchar (8 bit)
CheepinC_altera
Regular Contributor
6 years ago
Hi Jinfu, As I understand it, you have some inquiries related to implementing some of your add and multiplication function in FPGA logic instead of hard DSP block. Just wonder if you are coding the function using Verilog HDL or if you are using any specific IP? Also just would like to check with you which device and Quartus version that you are using? Take CV device as example, the following are ways that you can try to see if it helps: 1. If you are using IP, for your information, you may try with LPM_MULT and then select "Use logic elements" for implementation 2. If you are using your own Verilog HDL, you can try to specific "multstyle = dsp/logic" attribute to choose between soft logic or DSP block. You may refer to Insert Template -> Verilog HDL -> Synthesis Attributes -> multstyle Attribute for further details. Please let me know if there is any concern. Thank you. Best regards, Chee Pin
- zjinf
  Occasional Contributor
  6 years ago
  hi cpchan
  thanks for your help!
  my coding is opencl, the kernel is *.cl file , not verilog HDL or any IP, the aocl compiler translate to DSP or logic by itself !
  maybe any "compiler command" can help to do this when DSP over-utilization in theory , but i don't know the "compiler command"
CheepinC_altera
Regular Contributor
6 years ago
Hi Jinfu, Thanks for your update. Sorry as I am not sure if there is any similar setting for OpenCL. Just my thought, one of the workaround that you can try is to create a logic lock for a specific module to an area without DSP block to see if it helps If this does not work, would you mind to help duplicating a new Forum case and for the OpenCL inquiry and let me konw the case number? I will help to route to our OpenCL team for further assistance. Please let me know if there is any concern. Thank you. Best regards, Chee Pin
- zjinf
  Occasional Contributor
  6 years ago
  Hi cpchan
  For logic lock , it's OK for quartus, but i don't know how to use in aocl command in linux , if used in quartus, how to update to aocl ? any guide for this ?
  for "duplicating a new Forum case and for the OpenCL inquiry", where can i issue such kind topic in community forums? to which module ?
  Thanks for your help!
SBioo
Occasional Contributor
6 years ago
One reference example to avoid mapping MACs into the DSPs is the PipeCNN (you can find it on Github). They have wrapped their specific MAC, which is written in VHDL, into an OpenCL function. When you use this MAC function, you can see that it is only using FFs and LUTs, instead of DSPs.
CheepinC_altera
Regular Contributor
6 years ago
Thanks Saman for sharing. Hi jinfu, You can try to refer to the example by Saman. Regarding the OpenCL inquiry, if it is still required after you refer to the example design, you may just open a new case, with title relates to function in OpenCL to avoid mapping logic into DSP. You may then let me know the case number, I will help to engage OpenCL team to route it. Thank you.
CheepinC_altera
Regular Contributor
6 years ago
Hi jinfu, Just would like to follow up with you on this. Thank you.
zjinf
Occasional Contributor
6 years ago
hi cpchan
Sorry , cpchan , it confused me !
"You can try to refer to the example by Saman. " who is Saman ??? SBioo or not ??
if so , i will get it from Github!
if not , could you give me the example ??? i will try
Thank you very much !!
CheepinC_altera
Regular Contributor
6 years ago
Hi jinfu, Sorry for the confusion and typo. Yes, I am referring to example by SBioo. Sorry for the inconvenience.
CheepinC_altera
Regular Contributor
6 years ago
Hi, just would like to follow up with you on this. Thank you.
CheepinC_altera
Regular Contributor
6 years ago
Hi, As I understand it, it has been some time since I last heard from you. I would set this case to closed at this moment. Feel free to file a new case if you have any further question related to this request. Thank you for your understanding. Best regards, Chee Pin

Forum Discussion

How to maping add and multiplication calculation to FPGA logic element, not DSP unit in AOC environment

13 Replies

Recent Discussions

Error faced while executing on Agilex FPGA board....

AI Suite System Throughput Issue

Agilex 7 I-Series "aocl diagnose acl0" error following OFS

HLS Compiler 24.1 error - aocl-clang.exe - dll entry point not found

How Do I get the License for HLS?