How to maping add and multiplication calculation to FPGA logic element, not DSP unit in AOC environment

Hi Jinfu, As I understand it, you have some inquiries related to implementing some of your add and multiplication function in FPGA logic instead of hard DSP block. Just wonder if you are coding the function using Verilog HDL or if you are using any specific IP? Also just would like to check with you which device and Quartus version that you are using? Take CV device as example, the following are ways that you can try to see if it helps: 1. If you are using IP, for your information, you may try with LPM_MULT and then select "Use logic elements" for implementation 2. If you are using your own Verilog HDL, you can try to specific "multstyle = dsp/logic" attribute to choose between soft logic or DSP block. You may refer to Insert Template -> Verilog HDL -> Synthesis Attributes -> multstyle Attribute for further details. Please let me know if there is any concern. Thank you. Best regards, Chee Pin