New ContributorAN 754: MIPI D-PHY Solution with Cyclone V - questions on VCCIO/VCCDP/VREF connection
I am referring to the AN 754 (MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs) to acheive MIPI receive in Cyclone IV.
We can see in the document at Table 1, in FPGA I/O buffer mode for RX, that :
- For high-speed signaling mode, we can use differential I/O standard (LVDS25)
- For low-power signaling mode, we can use single-ended mode with HSTL12 or LVCMOS12 I/O standard
I would like your approval, for FPGA I/O buffer in RX mode only and for low-power signaling only, that we can use HSTL12 single-ended mode with the following connections for the same IO bank:
1) VCCIO=2.5V
2) VCCPD=2.5V
3) VREF=0.6V
4) and that there is no need for any VTT connection at all
I will be grateful if there is someone that can give me an approval on the connections detailed in items 1/2/3/4.
Thanks in advance.
Hi Aqid,
The AN754 refers to the Cyclone® IV, Cyclone V, Intel® Cyclone 10 LP, Intel MAX® 10.
But sorry for the typo, I am referring specicially to the Cyclone V.
Thanks for the approval, so it should be okay to connect with the requirement in 1/2/3:
1) VCCIO=2.5V
2) VCCPD=2.5V
3) VREF=0.6V
Regarding the VTT, I will follow the AN754 at Figure 1 (FPGA Unidirectional Receiver Implementation Block Diagram) or at Figure 3 (FPGA As Receiver HS-RX and LP-RX Modes IBIS Simulation Circuit) that is not using VTT at all.
THANKS A LOT FOR THE SUPPORT - I appreaciate a lot!!!
Regards,
David R.
