Forum Discussion
DdRd
New Contributor
1 year agoAN 754: MIPI D-PHY Solution with Cyclone V - questions on VCCIO/VCCDP/VREF connection
I am referring to the AN 754 (MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs) to acheive MIPI receive in Cyclone IV. We can see in the document at Table 1, in FPGA I/O b...
- 1 year ago
Hi Aqid,
The AN754 refers to the Cyclone® IV, Cyclone V, Intel® Cyclone 10 LP, Intel MAX® 10.
But sorry for the typo, I am referring specicially to the Cyclone V.
Thanks for the approval, so it should be okay to connect with the requirement in 1/2/3:
1) VCCIO=2.5V
2) VCCPD=2.5V
3) VREF=0.6V
Regarding the VTT, I will follow the AN754 at Figure 1 (FPGA Unidirectional Receiver Implementation Block Diagram) or at Figure 3 (FPGA As Receiver HS-RX and LP-RX Modes IBIS Simulation Circuit) that is not using VTT at all.
THANKS A LOT FOR THE SUPPORT - I appreaciate a lot!!!
Regards,
David R.
AqidAyman_Altera
Regular Contributor
1 year agoHello,
You wanted to connect HSTL-12 with the 1/2/3/4 requirement.
May I reconfirm with you with my understanding?
Regards,
Aqid
- DdRd1 year ago
New Contributor
Hi Aqid,
Yes, I confirm but HSTL-12 is in RX mode only.
Thanks.
Regards,
David R.