Forum Discussion
New ContributorAN 754: MIPI D-PHY Solution with Cyclone V - questions on VCCIO/VCCDP/VREF connection
Hi Aqid,
The AN754 refers to the Cyclone® IV, Cyclone V, Intel® Cyclone 10 LP, Intel MAX® 10.
But sorry for the typo, I am referring specicially to the Cyclone V.
Thanks for the approval, so it should be okay to connect with the requirement in 1/2/3:
1) VCCIO=2.5V
2) VCCPD=2.5V
3) VREF=0.6V
Regarding the VTT, I will follow the AN754 at Figure 1 (FPGA Unidirectional Receiver Implementation Block Diagram) or at Figure 3 (FPGA As Receiver HS-RX and LP-RX Modes IBIS Simulation Circuit) that is not using VTT at all.
THANKS A LOT FOR THE SUPPORT - I appreaciate a lot!!!
Regards,
David R.
New ContributorHi Aqid,
I would like you to double check because of the followings:
A) Per Intel document AN 754 (MIPI D-PHY Solution with Cyclone V), at Figure 3, there is no need for VTT.
B) Per same document AN 754, at Table 1, for FPGA I/O RX mode , for Low-power signaling mode and for HTSL-12 I/O standard, I/O voltage Supply is defined as 2.5V.
More than this, there is two notes (1) + (2) in the same table:
(1) The LVDS can co-exist in the same I/O bank as HSTL-12 when the FPGA is configured as input buffer in Cyclone® V devices.
(2) Input buffer for LVDS and HSTL-12 I/O standards are powered by VCCPD in Cyclone® V devices.
C) Also per Intel document CV-5V2 (Cyclone 5 Device Handbook), at Table 5-9, we can see that for 1.2V HSTL, VCCIO needed for input is VCCPD when VCCPD=2.5V
More than this, there is a note (11) in the same table:
(11) Input buffers for the SSTL, HSTL, Differential SSTL, Differential HSTL, LVDS, RSDS, Mini-LVDS, LVPECL,
HSUL, and Differential HSUL are powered by VCCPD
Thanks in advance.
Regards,
David R.
