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DdRd's avatar
DdRd
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1 year ago
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AN 754: MIPI D-PHY Solution with Cyclone V - questions on VCCIO/VCCDP/VREF connection

I am referring to the AN 754 (MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs) to acheive MIPI receive in Cyclone IV. We can see in the document at Table 1, in FPGA I/O b...
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  • DdRd's avatar
    DdRd
    1 year ago

    Hi Aqid,

    The AN754 refers to the Cyclone® IV, Cyclone V, Intel® Cyclone 10 LP, Intel MAX® 10.

    But sorry for the typo, I am referring specicially to the Cyclone V.

    Thanks for the approval, so it should be okay to connect with the requirement in 1/2/3:

    1) VCCIO=2.5V

    2) VCCPD=2.5V

    3) VREF=0.6V

    Regarding the VTT, I will follow the AN754 at Figure 1 (FPGA Unidirectional Receiver Implementation Block Diagram) or at Figure 3 (FPGA As Receiver HS-RX and LP-RX Modes IBIS Simulation Circuit) that is not using VTT at all.

    THANKS A LOT FOR THE SUPPORT - I appreaciate a lot!!!


    Regards,
    David R.

AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hello David,


Are you referring to Cyclone IV or Cyclone V? In your early description it mentioned on Cyclone IV. I really apologies if I understand it wrongly.


As if for Cyclone V, as your findings and pointing out the document, it should be okay to connect with the requirement in 1/2/3.


However, for the VTT, based on the CV-5V2 (Cyclone 5 Device Handbook), at Table 5-9, it should have connection to VTT=0.6V.

As for the Figure 3 you showed in AN754, it mentioned Cyclone IV.