Most Recentbuild issue with EDSNo HLS folder in Quartus Prime Pro 18.1Hi, I am trying to compile a design using QUARTUS PE 18.1. The targeted device is: 1SG280LN3F43E3VG (STRATIX10). Can any body help? JamilFatal Error: RUNTIME_0033 altera_mf.vhd (14081) Negative waveform time expressionGeneration of STP file for SignalTapUnable to run Intel HLS examplesALTASMI_PARALLEL in full synchro design. Can I use the same clock and edge (rising edge ) for clkin and the rest of the design?how can i eliminate this ----> Error (10482): VHDL error at Controller.vhd(17): object "UNSIGNED" is used but not declaredQuartus IP SDC filesI run the example as the HLS Compiler Getting Started Guide, but occur a warning LNK4088. Do you meet this warning?
