Forum Discussion
Occasional ContributorQuartus IP SDC files
Hello,
I'm using a Native PHY Transceiver in my Arria V design.
The IP is generated successfully - but I can't see any SDC files generated with it...do I have to write the timing constraints for it myself ?
7 Replies
KhaiChein_Y_IntelRegular Contributor
You may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/xcvr_user_guide.pdf (SDC Timing Constraints for Arria V Transceiver Native PHY IP Core )
- KhaiChein_Y_Intel
Hi Skon1,
The constraint for set_output_delay is not needed.
AbeFrequent Contributor
Hi,
When generating the PHY, click the EDA Options button and select the Generate Netlist option. Now, generate the PHY IP again. This time you will find the SDC generated.
- SKon1
Abe,
I checked the generate netlist box and regenerated the PHY - can't see any .SDC in the folder
- SKon1
KYeoh,
I see the SDC section for the Arria V.
Can't find any "set_output_delay" constraints for the data output.
It's basically only false paths...am I missing something ?
- SKon1
Did you see the document ?
I could see only false_path constrains in it...is that all that's required ?
- KhaiChein_Y_Intel
Yes. You just need to create clock and set false path to those asynchronous path.
