Most RecentWe have downloaded example design from below path: https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/arria-10-soc-development-kit.htmlHi i am implementing a HDMI module, everything went well when i am assigning the pins and simulating it i am getting an error and i am unable to get around.Weights of Max II CPLD and Max 10 FPGACyclone 10 GX Development Kit ddr problemCyclone 10 GX EMIF IP clockwe are using Arria 10 SoC FPGA Development Kit Board. generated example design and trying to do Ethernet test (PHY Serial loopback). we are getting CRC errorshow I can fix LABs requirements? I use the DE1_soc board, OS is ubuntu 18.04, and the intelFPGA_18.1 standard version. when I was trying to Compiling for FPGA then the following error generated.Why is the GTX clock output of the HPS running at 250 MHz?Chess digital clock with VHDL using FPGAFor the driver of a Modular Scatter-Gather DMA I need the header file "modular_sgdma_dispatcher.h". How can I get it, or what is the correct way to use "alt_msgdma_open" ?
