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burst read and write DDR2 using altmemphy
1) Need forum admin to help, I can not post any reply on below topic even use different browser. 2) answer to this topic: I set memory burst length = 8, and use half rate. Can I set local_size = 4, 8, 16 or even higher? Re:burst read and write DDR2 using altmemphy - Intel Communitiesproblem using altmemphy to read ddr2
1) need forum admin to help, I can not post any reply to below topic. Not sure if it's a website bug. 2) answer to below topic: Did the calibration finished properly in the design? > Yes, it's running on actual demo board, and the local_init_done = high What is the test_start signal does? > It's not related to ddr2. It's only a signal for my application after ddr2 ready. Is there a waitrequest signal in your design? > not used. How do you perform the write and read transaction? > you can look at below picture by ddr2 controller local interface, such as local_address, local_wdata, local_write_req, local_burstbegin..... I am using the exact sequence documented in intel guideline. 3) correct one information: ddr2 part number is MT47H32M16CC-3 https://community.intel.com/t5/Programmable-Devices/problem-using-altmemphy-to-read-ddr2/m-p/1382338burst read and write DDR2 using altmemphy
1) Need forum admin to help, I can not post any reply on below topic. 2) answer to this topic: I also attached code for you in the link. 3) correct one information, ddr2 ram is MT47H32M16CC-3. https://community.intel.com/t5/FPGA-Intellectual-Property/burst-read-and-write-DDR2-using-altmemphy/m-p/1382679burst read and write DDR2 using altmemphy
Device: EP4CE22F17C8 Memeory: Micron MT47H64M8CB-3 IP: altmemphy DDR2 local max Burst count = 64 Operation: 1 time burst write data -> 1 time burst read data issue: when set local size = 2, it works fine. when set local size = 16, we can not get data read out. (local_rdata_valid = low) Please see attachment for project code.problem using altmemphy to read ddr2
Device: EP4CE22F17C8 Memeory: Micron MT47H64M8CB-3 IP: altmemphy DDR2 Burst count = 16 I met a problem to read out data using altmemphy. 1) if I start with write operation ddr2 at first, after finished; then try to read data out of memory, then I can never get the data, the local_rdata_valid is always low. 2) if I don't do any write operation, try to read the data out of memory, I can get it successfully. I don't see any problem with my write process. What's wrong? Picture : write + read Picture only readRe: how to set timing constraints for source synchronous inputs
Thanks for your patience! I think I am close to the answer now. > for input, external device has their own clock, so we need to use virtual clock for timing constraint. > for output, for example, FPGA as SPI master to external device. The clock is provided by fpga, so there is no need to use virtual clock. > for output, for example, FPGA as SPI slave to external device. The clock is provided by external device, so we need to use virtual clock. > for uart communication, it's asynchronous communication, there is no clock. So we don't need to set any timing contraints. Please check if my above understanding is right or not. Thanks!
