jc_ddc
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Re: SSGDMA Bursting Manager Interface BAR
Hi Wincent, Thanks for your reply! I'm basing resource utilization off what's described on the resource utilization page of the MCMDA datasheet: https://www.intel.com/content/www/us/en/docs/programmable/847470/25-1-1/resource-utilization.html. The FPGA being used is the A5E013A, which only has 358 M20Ks available and a PCIe 4 x4 interface. Based off the resource utilization for the MCDMA, it seems we'd be unable to use with this part. Do you have any suggestions on how resource utilization for the MCDMA IP may be decreased? Thank you!380Views0likes1CommentSSGDMA Bursting Manager Interface BAR
Hello, I am working on a PCIe interface for an Altera Agilex 5 device. The PCIe interface will have two BARs defined for accessing user memory and registers without DMA (ex. memory mapped to BAR 1, configuration registers mapped to BAR 2). I intended to use the Bursting Manager (BAM) function of the Modular Scatter Gather DMA IP (MSGDMA) for the Agilex 5 since it allows multiple BARs to be mapped to the BAM. However, the MSDMA resource utilization exceeds that of the FPGA used for this design (it uses way more M20Ks than available). That brings me to the Scalable Scatter Gather DMA IP (SSGDMA) for the Agilex 5. The resource utilization of this IP fits within the constraints of the FPGA. However, it seems that the BAM for this IP can only be mapped to BAR 1... is this correct? Is there any way to map multiple BARs (like BAR 1 and 2) to the BAM of the SSGDMA? Thank you.Solved550Views0likes4CommentsRe: PCIe Example Design for Arrow EAGLE Board
I am experiencing the same issue. I was able to simulate the design example using Questa, but was unable to run in on hardware. I ran into issues mapping the two reset pins. There is no indication on which pin "p0_pin_perst_n_1_i_reset_n" needs to be connected to. I believe you're correct in changing the IO PLL Reference Clock to 25 MHz since this is what the Eagle board provides.1KViews1like0CommentsRe: Agilex 5 SSGDMA Example Design Generation Failed
Richard, Here are the results from testing: Long Paths Enabled, H2D MM = 0 -> Design example generation fails Long Paths Enabled, H2D MM = 1 -> Design example generation fails I was unable to disable long paths in the registry editor as I don't have permission to modify the registry. Would you suggest using Quartus in a Linux Virtual Machine to generate the design example?1.1KViews0likes0CommentsAgilex 5 SSGDMA Example Design Generation Failed
Hello, It seems I'm having an issue generating the example design for the Scalable Scatter-Gather DMA IP in PCIe mode (for Agilex 5 A5ED065BB32AE4SR0) in Quartus Prime Pro version 25.1 running on Windows 10 Pro. I’ve followed the instructions on generating the example design found here. Regarding the IP parameters, I was sure to match the number of H2D ST ports and D2H ST ports (1 each), and I only created 1 H2D MM port. I did not enable the BAM interface and I kept the application interface as 128-bit. When attempting to generate the example design, the system begins to generate it (takes about 5 minutes) but fails when copying a file to the temp director in AppData. I've attached the output from the generate example design screen. The error can be found on line 32. Is this a known issue in Quartus 25.1? I can attach my complete IP parameters if required. Thank you!Solved1.4KViews0likes9Comments