jc_ddc
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Cyclone V PCIe Reconfigure Busy Signal
Hello, I am working on a Cyclone V GT PCIe endpoint system in Platform Designer (Quartus version 24.1 Standard Edition). The system is based on the ep_g2x4 reference design (using the Avalon-MM Cyclone V Hard IP for PCI Express). I am trying to figure out what needs to be done with the "reconfig_busy" input to the hard IP. It seems the reconfiguration busy signal is already used between the transceiver reconfiguration IP and the PCIe reconfiguration driver IP. There are two mentions that I see of this signal in the Cyclone V Avalon-MM Interface for PCI Express manual (document 683494). The first mention is in the transceiver control signals section. busy_xcvr_reconfig - Input - When asserted, indicates that the a reconfiguration operation is in progress. In the Revision History, it mentions that the reconfig_busy signal connection between the PCIe IP core and the reconfig controller was removed. Removed reconfig_busy port from connect between PHY IP Core for PCI Express and the Transceiver Reconfiguration Controller in the Altera Transceiver Reconfiguration Controller Connectivity figure. The Transceiver Reconfiguration Controller drives reconfig_busy port to the Altera PCIe Reconfig Driver. In the Platform Designer reference design, this signal is exported, which doesn't help. This info doesn't help me determine how this signal needs to be driven. Since this is handled by the transceiver reconfiguration IP and the PCIe reconfiguration driver IP, is it sufficient to drive the reconfig_busy input to the PCIe IP to '0'? Thanks in advance.Solved48Views0likes2CommentsRe: SSGDMA Bursting Manager Interface BAR
Hi Wincent, Thanks for your reply! I'm basing resource utilization off what's described on the resource utilization page of the MCMDA datasheet: https://www.intel.com/content/www/us/en/docs/programmable/847470/25-1-1/resource-utilization.html. The FPGA being used is the A5E013A, which only has 358 M20Ks available and a PCIe 4 x4 interface. Based off the resource utilization for the MCDMA, it seems we'd be unable to use with this part. Do you have any suggestions on how resource utilization for the MCDMA IP may be decreased? Thank you!411Views0likes1CommentSSGDMA Bursting Manager Interface BAR
Hello, I am working on a PCIe interface for an Altera Agilex 5 device. The PCIe interface will have two BARs defined for accessing user memory and registers without DMA (ex. memory mapped to BAR 1, configuration registers mapped to BAR 2). I intended to use the Bursting Manager (BAM) function of the Modular Scatter Gather DMA IP (MSGDMA) for the Agilex 5 since it allows multiple BARs to be mapped to the BAM. However, the MSDMA resource utilization exceeds that of the FPGA used for this design (it uses way more M20Ks than available). That brings me to the Scalable Scatter Gather DMA IP (SSGDMA) for the Agilex 5. The resource utilization of this IP fits within the constraints of the FPGA. However, it seems that the BAM for this IP can only be mapped to BAR 1... is this correct? Is there any way to map multiple BARs (like BAR 1 and 2) to the BAM of the SSGDMA? Thank you.Solved603Views0likes4CommentsRe: PCIe Example Design for Arrow EAGLE Board
I am experiencing the same issue. I was able to simulate the design example using Questa, but was unable to run in on hardware. I ran into issues mapping the two reset pins. There is no indication on which pin "p0_pin_perst_n_1_i_reset_n" needs to be connected to. I believe you're correct in changing the IO PLL Reference Clock to 25 MHz since this is what the Eagle board provides.1.1KViews1like0CommentsRe: Agilex 5 SSGDMA Example Design Generation Failed
Richard, Here are the results from testing: Long Paths Enabled, H2D MM = 0 -> Design example generation fails Long Paths Enabled, H2D MM = 1 -> Design example generation fails I was unable to disable long paths in the registry editor as I don't have permission to modify the registry. Would you suggest using Quartus in a Linux Virtual Machine to generate the design example?1.1KViews0likes0Comments