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Maxime_Kanawasaki's avatar
Maxime_Kanawasaki
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4 months ago

PCIe Example Design for Arrow EAGLE Board

Hello !! I'm using Arrow Agilex-5 EAGLE Board with Device A5ED065BB32AE4SR0 with Q25.1 I've generated IP Core Example Design for Development Kit selected NONE. GTS AXI Streaming Intel FPGA IP ...
Fpga Devkit
jc_ddc's avatar
jc_ddc
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4 months ago

I am experiencing the same issue. I was able to simulate the design example using Questa, but was unable to run in on hardware.

I ran into issues mapping the two reset pins. There is no indication on which pin "p0_pin_perst_n_1_i_reset_n" needs to be connected to.

I believe you're correct in changing the IO PLL Reference Clock to 25 MHz since this is what the Eagle board provides.