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Fpga_Egr_2025

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Re: Nios IDE CPU Detection
Thanks for pointing that to me , yes i was able to generate bsp as per document "AN 985: Nios® V Processor Tutorial" , But now i am stuck on this step : See also attached my Niosv command console messages : Any idea why niosv shell cannot recognize these switches ? Thanks
2 months ago Place Nios® System
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Nios IDE CPU Detection
Hi, I am trying to create bsp and software for Nios V , using Eclipse IDE. When specifying a new projcet and its .sopc file i see message CPU not detected. And i also see message the NIOS_EDS environment variable not set. See screen shot attached . I verified via command prompt the environment variable is set and can be verified. Also i noticed there are no examples installed at this path : C:\intelFPGA_lite\24.1std\nios2eds Looking forward to resolve these issues, Thanks, Regards,
2 months ago Place Nios® System
Nios Cpu
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UVM Questasim simulation
HI , I am trying to simulate a generic ALU in Systemverilog UVM test environment . My add_i is random input signal , but when i open my wave i dont see it toggling , but the display function reports it is being toggled ? here are my files : // alu package file // package alu_pkg; //----Transaction Class---- class transaction; //declaring the transaction items rand bit [3:0] a; rand bit [3:0] b; bit [6:0] c; rand bit add_i; function void display(string name); $display("-------------------------"); $display("- %s ",name); $display("-------------------------"); $display("- a = %0d, b = %0d",a,b); $display("- c = %0d",c); $display("-------------------------"); $display("-- ADD = %b --",add_i); endfunction endclass //---------------------------------------// //-----------Driver Class------------------ class driver; //used to count the number of transactions int no_transactions; //creating virtual interface handle virtual intf_alu#(.WORD_LENGTH(4)) vif; //creating mailbox handle mailbox gen2driv; //constructor function new(virtual intf_alu vif,mailbox gen2driv); //getting the interface this.vif = vif; //getting the mailbox handles from environment this.gen2driv = gen2driv; endfunction //Reset task, Reset the Interface signals to default/initial values task reset; wait(vif.reset); $display("[ DRIVER ] ----- Reset Started -----"); vif.a <= 0; vif.b <= 0; vif.valid <= 0; vif.add_i <= 0; vif.mul_i <= 0; vif.sub_i <= 0; vif.div_i <= 0; vif.and_i <= 0; vif.or_i <= 0; vif.xor_i <= 0; wait(!vif.reset); $display("[ DRIVER ] ----- Reset Ended -----"); endtask //drivers the transaction items to interface signals task main; forever begin transaction trans; gen2driv.get(trans); @(posedge vif.clk); vif.valid <= 1; //vif.add_i <= 1; vif.a <= trans.a; vif.b <= trans.b; @(posedge vif.clk); vif.valid <= 0; //vif.add_i <= 0; trans.c = vif.c; @(posedge vif.clk); trans.display("[ Driver ]"); no_transactions++; end endtask endclass //---------------------------------------// //----Generator Class------------------ class generator; //declaring transaction class rand transaction trans; //repeat count, to specify number of items to generate int repeat_count; //mailbox, to generate and send the packet to driver mailbox gen2driv; //event, to indicate the end of transaction generation event ended; //constructor function new(mailbox gen2driv); //getting the mailbox handle from env, in order to share the transaction packet between the generator and driver, the same mailbox is shared between both. this.gen2driv = gen2driv; endfunction //main task, generates(create and randomizes) the repeat_count number of transaction packets and puts into mailbox task main(); repeat(repeat_count) begin trans = new(); if( !trans.randomize() ) $fatal("Gen:: trans randomization failed"); trans.display("[ Generator ]"); gen2driv.put(trans); end -> ended; //triggering indicatesthe end of generation endtask endclass //---------------------------------------// //----Environment Class------------------ class environment; //generator and driver instance generator gen; driver driv; //mailbox handle's mailbox gen2driv; //virtual interface virtual intf_alu#(.WORD_LENGTH(4)) vif; //constructor function new(virtual intf_alu vif); //get the interface from test this.vif = vif; //creating the mailbox (Same handle will be shared across generator and driver) gen2driv = new(); //creating generator and driver gen = new(gen2driv); driv = new(vif,gen2driv); endfunction // task pre_test(); driv.reset(); endtask task test(); fork gen.main(); driv.main(); join_any endtask task post_test(); wait(gen.ended.triggered); wait(gen.repeat_count == driv.no_transactions); endtask //run task task run; pre_test(); test(); post_test(); $finish; endtask endclass //---------------------------------------// endpackage
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4 months ago Place FPGA Device
Core Logic
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Re: Gate Level Simulation
Hi Alan, Thanks for your reply , i have to stick to VHDL implementation i will search or modify the code . Thanks, Regards,
1 year ago Place Boards & Dev Kits
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Re: Gate Level Simulation
Hi Alan, I modified the tb code as follows : entity UART_TB is end UART_TB; LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.numeric_std.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use IEEE.math_real.all; architecture Testing_UART of UART_TB is -- TB constants -- constant LEDG_WIDTH : integer := 9; constant LEDR_WIDTH : integer := 18; constant SW_WIDTH : integer := 18; constant GPIO_WIDTH : integer := 37; ---------------------------------- component UART_Top IS -- generic (LEDG_WIDTH : integer := 9; -- LEDR_WIDTH : integer := 18; -- SW_WIDTH : integer := 18; -- GPIO_WIDTH : integer := 37 -- ); PORT ( CLOCK_50 : IN STD_LOGIC; UART_TXD : OUT STD_LOGIC; -- Switches SW : IN STD_LOGIC_VECTOR(SW_WIDTH-1 DOWNTO 0); -- Push Buttons KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- LEDs LEDG : OUT STD_LOGIC_VECTOR(LEDG_WIDTH-1 DOWNTO 0); LEDR : OUT STD_LOGIC_VECTOR(LEDR_WIDTH-1 DOWNTO 0); GPIO : INOUT STD_LOGIC_VECTOR(GPIO_WIDTH-1 DOWNTO 0) ); end component; -- signal Clock_50_tb, UART_TX_tb : STD_LOGIC; signal LEDR_tb, SW_tb : STD_LOGIC_VECTOR(SW_WIDTH-1 DOWNTO 0); signal LEDG_tb : STD_LOGIC_VECTOR(LEDG_WIDTH-1 DOWNTO 0); signal KEY_tb : STD_LOGIC_VECTOR(3 DOWNTO 0); signal GPIO_tb : STD_LOGIC_VECTOR(GPIO_WIDTH-1 DOWNTO 0); ------------------------------------------------------------------- BEGIN -- instantiate the component under test UUT: UART_Top --generic map( LEDG_WIDTH => LEDG_WIDTH, -- LEDR_WIDTH => LEDR_WIDTH, -- SW_WIDTH => SW_WIDTH, -- GPIO_WIDTH => GPIO_WIDTH -- ) PORT MAP( CLOCK_50 => Clock_50_tb, UART_TXD => UART_TX_tb, SW => SW_tb, KEY => KEY_tb, LEDG => LEDG_tb, LEDR => LEDR_tb, GPIO => GPIO_tb ); ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- --------- Questasim Error messages ------------------------------------ vsim -t ps -L work UART_TB # vsim -t ps -L work UART_TB # Start time: 11:36:33 on Aug 27,2025 # ** Note: (vsim-3812) Design is being optimized... # ** Error: C:/intelFPGA_lite/24.1std/quartus/qdesigns/HW_tested_verified_prjs/UART_TX_HW_test/UART_TB.vhd(58): (vopt-1134) Incompatible modes for port "UART_TXD" in component "UART_Top" when binding to entity "UART_Top". # ** Error: C:/intelFPGA_lite/24.1std/quartus/qdesigns/HW_tested_verified_prjs/UART_TX_HW_test/UART_TB.vhd(58): (vopt-1134) Incompatible modes for port "LEDG" in component "UART_Top" when binding to entity "UART_Top". # ** Error: C:/intelFPGA_lite/24.1std/quartus/qdesigns/HW_tested_verified_prjs/UART_TX_HW_test/UART_TB.vhd(58): (vopt-1134) Incompatible modes for port "LEDR" in component "UART_Top" when binding to entity "UART_Top". # ** Error: C:/intelFPGA_lite/24.1std/quartus/qdesigns/HW_tested_verified_prjs/UART_TX_HW_test/UART_TB.vhd(58): (vopt-1134) Incompatible modes for port "GPIO" in component "UART_Top" when binding to entity "UART_Top". # Optimization failed # ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=8, Warnings=1. # Error loading design # Error: Error loading design # Pausing macro execution # MACRO ./gate_sim.do PAUSED at line 2 Now it is detecting incompatible modes for ports. Thanks, Regards
1 year ago Place Boards & Dev Kits
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Re: Gate Level Simulation
Hi Alan, Thanks for pointing that out , i did corrected the UUT binding. But i am still getting the same error. I tried deleting the UART_Top.vho file , compiled the files again in quartus. Simulated again in RTL and then Gate level but Questasim is still stuck at this error . --------------------------------------------------- entity UART_TB is end UART_TB; LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.numeric_std.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use IEEE.math_real.all; architecture Testing_UART of UART_TB is -- TB constants -- constant LEDG_WIDTH : integer := 9; constant LEDR_WIDTH : integer := 18; constant SW_WIDTH : integer := 18; constant GPIO_WIDTH : integer := 37; ---------------------------------- component UART_Top IS generic (LEDG_WIDTH : integer := 9; LEDR_WIDTH : integer := 18; SW_WIDTH : integer := 18; GPIO_WIDTH : integer := 37 ); PORT ( CLOCK_50 : IN STD_LOGIC; UART_TXD : OUT STD_LOGIC; -- Switches SW : IN STD_LOGIC_VECTOR(SW_WIDTH-1 DOWNTO 0); -- Push Buttons KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- LEDs LEDG : OUT STD_LOGIC_VECTOR(LEDG_WIDTH-1 DOWNTO 0); LEDR : OUT STD_LOGIC_VECTOR(LEDR_WIDTH-1 DOWNTO 0); GPIO : INOUT STD_LOGIC_VECTOR(GPIO_WIDTH-1 DOWNTO 0) ); end component; -- signal Clock_50_tb, UART_TX_tb : STD_LOGIC; signal LEDR_tb, SW_tb : STD_LOGIC_VECTOR(SW_WIDTH-1 DOWNTO 0); signal LEDG_tb : STD_LOGIC_VECTOR(LEDG_WIDTH-1 DOWNTO 0); signal KEY_tb : STD_LOGIC_VECTOR(3 DOWNTO 0); signal GPIO_tb : STD_LOGIC_VECTOR(GPIO_WIDTH-1 DOWNTO 0); ------------------------------------------------------------------- BEGIN -- instantiate the component under test UUT: UART_Top generic map( LEDG_WIDTH => LEDG_WIDTH, LEDR_WIDTH => LEDR_WIDTH, SW_WIDTH => SW_WIDTH, GPIO_WIDTH => GPIO_WIDTH ) PORT MAP( CLOCK_50 => Clock_50_tb, UART_TXD => UART_TX_tb, SW => SW_tb, KEY => KEY_tb, LEDG => LEDG_tb, LEDR => LEDR_tb, GPIO => GPIO_tb ); ----------------------------------------------------------------------- --Questasim Error ------------------------ # vsim -t ps -L work UART_TB # vsim -t ps -L work UART_TB # Start time: 17:36:29 on Aug 26,2025 # ** Note: (vsim-3812) Design is being optimized... # ** Error (suppressible): C:/intelFPGA_lite/24.1std/quartus/qdesigns/HW_tested_verified_prjs/UART_TX_HW_test/UART_TB.vhd(58): (vopt-1271) Bad default binding for component instance "UUT: UART_Top". # (Component generic "GPIO_WIDTH" is not on the entity "work.UART_Top".) # (Entity is selected because it is in the same library as the design unit that contains the component.) # Optimization failed # ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=2, Warnings=1. # Error loading design # Error: Error loading design # Pausing macro execution # MACRO ./gate_sim.do PAUSED at line 2
1 year ago Place Boards & Dev Kits
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Gate Level Simulation
Hi , I am trying to run gate level simulation for my uart implementation, but for some reason the Questasim complains about UUT binding not correct . Although in RTL simulation it works fine. See below my UART Top and UART TB code. I also tried running a TCL recommended in the Intel Quartus Simulation guide but it comes up with the same error. -- UART TOP -- LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.numeric_std.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use IEEE.math_real.all; -- -- Top level module ENTITY UART_Top IS generic (LEDG_WIDTH : integer := 9; LEDR_WIDTH : integer := 18; SW_WIDTH : integer := 18; GPIO_WIDTH : integer := 37 ); PORT ( CLOCK_50 : IN STD_LOGIC; UART_TXD : OUT STD_LOGIC; -- Switches SW : IN STD_LOGIC_VECTOR(SW_WIDTH-1 DOWNTO 0); -- Push Buttons KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- LEDs LEDG : OUT STD_LOGIC_VECTOR(LEDG_WIDTH-1 DOWNTO 0); LEDR : OUT STD_LOGIC_VECTOR(LEDR_WIDTH-1 DOWNTO 0); GPIO : INOUT STD_LOGIC_VECTOR(GPIO_WIDTH-1 DOWNTO 0) ); end UART_Top; architecture Uart_tx_STRUCTURE of UART_Top is -- UART Transmitter -- component TX is port ( clk : IN STD_LOGIC; Reset : IN STD_LOGIC; Start : IN STD_LOGIC; Baud_Rate : IN INTEGER; Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0); Done : OUT STD_LOGIC; Running : OUT STD_LOGIC; TX_Data : OUT STD_LOGIC); end component TX; ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- -- UART Test bench -- entity UART_TB is end UART_TB; LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.numeric_std.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use IEEE.math_real.all; architecture Testing_UART of UART_TB is -- TB constants -- constant LEDG_WIDTH : integer := 9; constant LEDR_WIDTH : integer := 18; constant SW_WIDTH : integer := 18; constant GPIO_WIDTH : integer := 37; ---------------------------------- component UART_Top IS generic (LEDG_WIDTH : integer := 9; LEDR_WIDTH : integer := 18; SW_WIDTH : integer := 18; GPIO_WIDTH : integer := 37 ); PORT ( CLOCK_50: IN STD_LOGIC; -- Switches SW : IN STD_LOGIC_VECTOR(SW_WIDTH-1 DOWNTO 0); -- Push Buttons KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- LEDs LEDG : OUT STD_LOGIC_VECTOR(LEDG_WIDTH-1 DOWNTO 0); LEDR : OUT STD_LOGIC_VECTOR(LEDR_WIDTH-1 DOWNTO 0); GPIO : INOUT STD_LOGIC_VECTOR(GPIO_WIDTH-1 DOWNTO 0) ); end component; ------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------ -- gate sim TCL -- vcom -2008 UART_Top.vho vsim -t ps -L work UART_TB add wave -r /* run -all quit --------------------------------------------------------- --------------------------------------------------------- -- Error -- Errors: 0, Warnings: 0 # vsim -t ps -L work UART_TB # vsim -t ps -L work UART_TB # Start time: 10:17:46 on Aug 26,2025 # ** Note: (vsim-3812) Design is being optimized... # ** Error (suppressible): C:/intelFPGA_lite/24.1std/quartus/qdesigns/HW_tested_verified_prjs/UART_TX_HW_test/UART_TB.vhd(56): (vopt-1271) Bad default binding for component instance "UUT: UART_Top". # (Component generic "GPIO_WIDTH" is not on the entity "work.UART_Top".) # (Entity is selected because it is in the same library as the design unit that contains the component.) # Optimization failed # ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=2, Warnings=1. # Error loading design # Error: Error loading design # Pausing macro execution # MACRO ./gate_sim.do PAUSED at line 2
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1 year ago Place Boards & Dev Kits
Fpga Devkit
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Re: Ashling RiscV NiosV errors
Hi , i was able to compile my design for the NiosV targeting CycloneIVE FPGA on DE2-115 board p/n : EP4CE115F29C7. But now the JTAG debugging is not working, i searched the forums for that issue and it seems that clock speed has to be double of what system clock is i.e 50Mhz . See screen shot attached.
1 year ago Place Nios® System
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Re: Ashling RiscV NiosV errors
what do you mean exporting the path variable ? how to do it
1 year ago Place Nios® System
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Re: Ashling RiscV NiosV errors
my user variable path :
1 year ago Place Nios® System
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