Fpga_Egr_2025
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Ashling RiscV NiosV errors
Hi I am trying to compile a simple hello world on NiosV targeting a CycloneIVE FPGA on DE2-115 board p/n : EP4CE115F29C7. But when i build project in Ashling RiscFree i get these errors which i dont have any idea what these referring to : Below i am pasting the complete system.h file : /* * system.h - SOPC Builder system and BSP software package information * * Machine generated for CPU 'Nios_gen_purpose' in SOPC Builder design 'SOC_uart' * SOPC Builder design path: ../../SOC_uart.sopcinfo * * Generated: Tue May 27 13:03:27 PKT 2025 */ /* * DO NOT MODIFY THIS FILE * * Changing this file will have subtle consequences * which will almost certainly lead to a nonfunctioning * system. If you do modify this file, be aware that your * changes will be overwritten and lost when this file * is generated again. * * DO NOT MODIFY THIS FILE */ /* * License Agreement * * Copyright (c) 2008 * Altera Corporation, San Jose, California, USA. * All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * This agreement shall be governed in all respects by the laws of the State * of California and by the laws of the United States of America. */ #ifndef __SYSTEM_H_ #define __SYSTEM_H_ /* Include definitions from linker script generator */ #include "linker.h" /* * CPU configuration * */ #define ALT_CPU_ARCHITECTURE "intel_niosv_g" #define ALT_CPU_CLIC_EN 0 #define ALT_CPU_CPU_FREQ 50000000u #define ALT_CPU_DATA_ADDR_WIDTH 0x20 #define ALT_CPU_DCACHE_LINE_SIZE 32 #define ALT_CPU_DCACHE_LINE_SIZE_LOG2 5 #define ALT_CPU_DCACHE_SIZE 4096 #define ALT_CPU_FREQ 50000000 #define ALT_CPU_HAS_CSR_SUPPORT 1 #define ALT_CPU_HAS_DEBUG_STUB #define ALT_CPU_ICACHE_LINE_SIZE 32 #define ALT_CPU_ICACHE_LINE_SIZE_LOG2 5 #define ALT_CPU_ICACHE_SIZE 4096 #define ALT_CPU_INST_ADDR_WIDTH 0x20 #define ALT_CPU_INT_MODE 0 #define ALT_CPU_MTIME_OFFSET 0x00030000 #define ALT_CPU_NAME "Nios_gen_purpose" #define ALT_CPU_NIOSV_CORE_VARIANT 3 #define ALT_CPU_NUM_GPR 32 #define ALT_CPU_NUM_SRF_BANKS 1 #define ALT_CPU_RESET_ADDR 0x00000000 #define ALT_CPU_TICKS_PER_SEC NIOSV_INTERNAL_TIMER_TICKS_PER_SECOND #define ALT_CPU_TIMER_DEVICE_TYPE 2 /* * CPU configuration (with legacy prefix - don't use these anymore) * */ #define BANTAMLAKE_CLIC_EN 0 #define BANTAMLAKE_CPU_FREQ 50000000u #define BANTAMLAKE_DATA_ADDR_WIDTH 0x20 #define BANTAMLAKE_DCACHE_LINE_SIZE 32 #define BANTAMLAKE_DCACHE_LINE_SIZE_LOG2 5 #define BANTAMLAKE_DCACHE_SIZE 4096 #define BANTAMLAKE_HAS_CSR_SUPPORT 1 #define BANTAMLAKE_HAS_DEBUG_STUB #define BANTAMLAKE_ICACHE_LINE_SIZE 32 #define BANTAMLAKE_ICACHE_LINE_SIZE_LOG2 5 #define BANTAMLAKE_ICACHE_SIZE 4096 #define BANTAMLAKE_INST_ADDR_WIDTH 0x20 #define BANTAMLAKE_INT_MODE 0 #define BANTAMLAKE_MTIME_OFFSET 0x00030000 #define BANTAMLAKE_NIOSV_CORE_VARIANT 3 #define BANTAMLAKE_NUM_GPR 32 #define BANTAMLAKE_NUM_SRF_BANKS 1 #define BANTAMLAKE_RESET_ADDR 0x00000000 #define BANTAMLAKE_TICKS_PER_SEC NIOSV_INTERNAL_TIMER_TICKS_PER_SECOND #define BANTAMLAKE_TIMER_DEVICE_TYPE 2 /* * Define for each module class mastered by the CPU * */ #define __ALTERA_AVALON_JTAG_UART #define __ALTERA_AVALON_ONCHIP_MEMORY2 #define __ALTERA_AVALON_PIO #define __ALTERA_AVALON_SYSID_QSYS #define __ALTERA_AVALON_UART #define __INTEL_NIOSV_G /* * GPIO configuration * */ #define ALT_MODULE_CLASS_GPIO altera_avalon_pio #define GPIO_BASE 0x100000 #define GPIO_BIT_CLEARING_EDGE_REGISTER 0 #define GPIO_BIT_MODIFYING_OUTPUT_REGISTER 0 #define GPIO_CAPTURE 0 #define GPIO_DATA_WIDTH 32 #define GPIO_DO_TEST_BENCH_WIRING 0 #define GPIO_DRIVEN_SIM_VALUE 0 #define GPIO_EDGE_TYPE "NONE" #define GPIO_FREQ 50000000 #define GPIO_HAS_IN 0 #define GPIO_HAS_OUT 0 #define GPIO_HAS_TRI 1 #define GPIO_IRQ -1 #define GPIO_IRQ_INTERRUPT_CONTROLLER_ID -1 #define GPIO_IRQ_TYPE "NONE" #define GPIO_NAME "/dev/GPIO" #define GPIO_RESET_VALUE 0 #define GPIO_SPAN 16 #define GPIO_TYPE "altera_avalon_pio" /* * Nios_gen_purpose_dm_agent configuration * */ #define ALT_MODULE_CLASS_Nios_gen_purpose_dm_agent intel_niosv_g #define NIOS_GEN_PURPOSE_DM_AGENT_BASE 0x20000 #define NIOS_GEN_PURPOSE_DM_AGENT_CLIC_EN 0 #define NIOS_GEN_PURPOSE_DM_AGENT_CPU_FREQ 50000000u #define NIOS_GEN_PURPOSE_DM_AGENT_DATA_ADDR_WIDTH 0x20 #define NIOS_GEN_PURPOSE_DM_AGENT_DCACHE_LINE_SIZE 32 #define NIOS_GEN_PURPOSE_DM_AGENT_DCACHE_LINE_SIZE_LOG2 5 #define NIOS_GEN_PURPOSE_DM_AGENT_DCACHE_SIZE 4096 #define NIOS_GEN_PURPOSE_DM_AGENT_HAS_CSR_SUPPORT 1 #define NIOS_GEN_PURPOSE_DM_AGENT_HAS_DEBUG_STUB #define NIOS_GEN_PURPOSE_DM_AGENT_ICACHE_LINE_SIZE 32 #define NIOS_GEN_PURPOSE_DM_AGENT_ICACHE_LINE_SIZE_LOG2 5 #define NIOS_GEN_PURPOSE_DM_AGENT_ICACHE_SIZE 4096 #define NIOS_GEN_PURPOSE_DM_AGENT_INST_ADDR_WIDTH 0x20 #define NIOS_GEN_PURPOSE_DM_AGENT_INTERRUPT_CONTROLLER_ID 0 #define NIOS_GEN_PURPOSE_DM_AGENT_INT_MODE 0 #define NIOS_GEN_PURPOSE_DM_AGENT_IRQ -1 #define NIOS_GEN_PURPOSE_DM_AGENT_IRQ_INTERRUPT_CONTROLLER_ID -1 #define NIOS_GEN_PURPOSE_DM_AGENT_MTIME_OFFSET 0x00030000 #define NIOS_GEN_PURPOSE_DM_AGENT_NAME "/dev/Nios_gen_purpose_dm_agent" #define NIOS_GEN_PURPOSE_DM_AGENT_NIOSV_CORE_VARIANT 3 #define NIOS_GEN_PURPOSE_DM_AGENT_NUM_GPR 32 #define NIOS_GEN_PURPOSE_DM_AGENT_NUM_SRF_BANKS 1 #define NIOS_GEN_PURPOSE_DM_AGENT_RESET_ADDR 0x00000000 #define NIOS_GEN_PURPOSE_DM_AGENT_SPAN 65536 #define NIOS_GEN_PURPOSE_DM_AGENT_TICKS_PER_SEC NIOSV_INTERNAL_TIMER_TICKS_PER_SECOND #define NIOS_GEN_PURPOSE_DM_AGENT_TIMER_DEVICE_TYPE 2 #define NIOS_GEN_PURPOSE_DM_AGENT_TYPE "intel_niosv_g" /* * Nios_gen_purpose_timer_sw_agent configuration * */ #define ALT_MODULE_CLASS_Nios_gen_purpose_timer_sw_agent intel_niosv_g #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_BASE 0x30000 #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_CLIC_EN 0 #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_CPU_FREQ 50000000u #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_DATA_ADDR_WIDTH 0x20 #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_DCACHE_LINE_SIZE 32 #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_DCACHE_LINE_SIZE_LOG2 5 #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_DCACHE_SIZE 4096 #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_HAS_CSR_SUPPORT 1 #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_HAS_DEBUG_STUB #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_ICACHE_LINE_SIZE 32 #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_ICACHE_LINE_SIZE_LOG2 5 #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_ICACHE_SIZE 4096 #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_INST_ADDR_WIDTH 0x20 #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_INTERRUPT_CONTROLLER_ID 0 #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_INT_MODE 0 #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_IRQ -1 #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_IRQ_INTERRUPT_CONTROLLER_ID -1 #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_MTIME_OFFSET 0x00030000 #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_NAME "/dev/Nios_gen_purpose_timer_sw_agent" #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_NIOSV_CORE_VARIANT 3 #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_NUM_GPR 32 #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_NUM_SRF_BANKS 1 #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_RESET_ADDR 0x00000000 #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_SPAN 64 #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_TICKS_PER_SEC NIOSV_INTERNAL_TIMER_TICKS_PER_SECOND #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_TIMER_DEVICE_TYPE 2 #define NIOS_GEN_PURPOSE_TIMER_SW_AGENT_TYPE "intel_niosv_g" /* * System configuration * */ #define ALT_DEVICE_FAMILY "Cyclone IV E" #define ALT_ENHANCED_INTERRUPT_API_PRESENT #define ALT_IRQ_BASE NULL #define ALT_LOG_PORT "/dev/null" #define ALT_LOG_PORT_BASE 0x0 #define ALT_LOG_PORT_DEV null #define ALT_LOG_PORT_TYPE "" #define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0 #define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1 #define ALT_NUM_INTERRUPT_CONTROLLERS 1 #define ALT_STDERR "/dev/jtag_uart" #define ALT_STDERR_BASE 0x30040 #define ALT_STDERR_DEV jtag_uart #define ALT_STDERR_IS_JTAG_UART #define ALT_STDERR_PRESENT #define ALT_STDERR_TYPE "altera_avalon_jtag_uart" #define ALT_STDIN "/dev/jtag_uart" #define ALT_STDIN_BASE 0x30040 #define ALT_STDIN_DEV jtag_uart #define ALT_STDIN_IS_JTAG_UART #define ALT_STDIN_PRESENT #define ALT_STDIN_TYPE "altera_avalon_jtag_uart" #define ALT_STDOUT "/dev/jtag_uart" #define ALT_STDOUT_BASE 0x30040 #define ALT_STDOUT_DEV jtag_uart #define ALT_STDOUT_IS_JTAG_UART #define ALT_STDOUT_PRESENT #define ALT_STDOUT_TYPE "altera_avalon_jtag_uart" #define ALT_SYSID_BASE NIOS_SYSID_BASE #define ALT_SYSID_ID NIOS_SYSID_ID #define ALT_SYSTEM_NAME "SOC_uart" #define ALT_SYS_CLK_TICKS_PER_SEC ALT_CPU_TICKS_PER_SEC #define ALT_TIMESTAMP_CLK_TIMER_DEVICE_TYPE ALT_CPU_TIMER_DEVICE_TYPE /* * Uart_transciever configuration * */ #define ALT_MODULE_CLASS_Uart_transciever altera_avalon_uart #define UART_TRANSCIEVER_BASE 0x80000 #define UART_TRANSCIEVER_BAUD 9600 #define UART_TRANSCIEVER_DATA_BITS 8 #define UART_TRANSCIEVER_FIXED_BAUD 1 #define UART_TRANSCIEVER_FREQ 50000000 #define UART_TRANSCIEVER_IRQ 1 #define UART_TRANSCIEVER_IRQ_INTERRUPT_CONTROLLER_ID 0 #define UART_TRANSCIEVER_NAME "/dev/Uart_transciever" #define UART_TRANSCIEVER_PARITY 'N' #define UART_TRANSCIEVER_SIM_CHAR_STREAM "" #define UART_TRANSCIEVER_SIM_TRUE_BAUD 0 #define UART_TRANSCIEVER_SPAN 32 #define UART_TRANSCIEVER_STOP_BITS 1 #define UART_TRANSCIEVER_SYNC_REG_DEPTH 2 #define UART_TRANSCIEVER_TYPE "altera_avalon_uart" #define UART_TRANSCIEVER_USE_CTS_RTS 0 #define UART_TRANSCIEVER_USE_EOP_REGISTER 0 /* * hal2 configuration * */ #define ALT_MAX_FD 32 #define ALT_SYS_CLK NIOS_GEN_PURPOSE #define ALT_TIMESTAMP_CLK NIOS_GEN_PURPOSE #define INTEL_FPGA_DFL_START_ADDRESS 0xffffffffffffffff #define INTEL_FPGA_USE_DFL_WALKER 0 /* * intel_niosv_g_hal_driver configuration * */ #define NIOSV_INTERNAL_TIMER_TICKS_PER_SECOND 1000 /* * jtag_uart configuration * */ #define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart #define JTAG_UART_BASE 0x30040 #define JTAG_UART_IRQ 0 #define JTAG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0 #define JTAG_UART_NAME "/dev/jtag_uart" #define JTAG_UART_READ_DEPTH 64 #define JTAG_UART_READ_THRESHOLD 8 #define JTAG_UART_SPAN 8 #define JTAG_UART_TYPE "altera_avalon_jtag_uart" #define JTAG_UART_WRITE_DEPTH 64 #define JTAG_UART_WRITE_THRESHOLD 8 /* * nios_sysid configuration * */ #define ALT_MODULE_CLASS_nios_sysid altera_avalon_sysid_qsys #define NIOS_SYSID_BASE 0x30000 #define NIOS_SYSID_ID 6512 #define NIOS_SYSID_IRQ -1 #define NIOS_SYSID_IRQ_INTERRUPT_CONTROLLER_ID -1 #define NIOS_SYSID_NAME "/dev/nios_sysid" #define NIOS_SYSID_SPAN 8 #define NIOS_SYSID_TIMESTAMP 1748332863 #define NIOS_SYSID_TYPE "altera_avalon_sysid_qsys" /* * onchip_memory2 configuration * */ #define ALT_MODULE_CLASS_onchip_memory2 altera_avalon_onchip_memory2 #define ONCHIP_MEMORY2_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0 #define ONCHIP_MEMORY2_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 #define ONCHIP_MEMORY2_BASE 0x0 #define ONCHIP_MEMORY2_CONTENTS_INFO "" #define ONCHIP_MEMORY2_DUAL_PORT 0 #define ONCHIP_MEMORY2_GUI_RAM_BLOCK_TYPE "AUTO" #define ONCHIP_MEMORY2_INIT_CONTENTS_FILE "SOC_uart_onchip_memory2" #define ONCHIP_MEMORY2_INIT_MEM_CONTENT 1 #define ONCHIP_MEMORY2_INSTANCE_ID "NONE" #define ONCHIP_MEMORY2_IRQ -1 #define ONCHIP_MEMORY2_IRQ_INTERRUPT_CONTROLLER_ID -1 #define ONCHIP_MEMORY2_NAME "/dev/onchip_memory2" #define ONCHIP_MEMORY2_NON_DEFAULT_INIT_FILE_ENABLED 0 #define ONCHIP_MEMORY2_RAM_BLOCK_TYPE "AUTO" #define ONCHIP_MEMORY2_READ_DURING_WRITE_MODE "DONT_CARE" #define ONCHIP_MEMORY2_SINGLE_CLOCK_OP 0 #define ONCHIP_MEMORY2_SIZE_MULTIPLE 1 #define ONCHIP_MEMORY2_SIZE_VALUE 131072 #define ONCHIP_MEMORY2_SPAN 131072 #define ONCHIP_MEMORY2_TYPE "altera_avalon_onchip_memory2" #define ONCHIP_MEMORY2_WRITABLE 1 #endif /* __SYSTEM_H_ */ Can anyone help me resolve this issue . Thanks Regards
