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Fpga_Egr_2025

Occasional Contributor

4 months ago

Solved

Gate Level Simulation

Hi ,

I am trying to run gate level simulation for my uart implementation, but for some reason the Questasim complains about UUT binding not correct . Although in RTL simulation it works fine.

See below my UART Top and UART TB code. I also tried running a TCL recommended in the Intel Quartus Simulation guide but it comes up with the same error.

-- UART TOP --

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

USE ieee.numeric_std.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

use IEEE.math_real.all;

-- Top level module

ENTITY UART_Top IS

generic (LEDG_WIDTH : integer := 9;

LEDR_WIDTH : integer := 18;

SW_WIDTH : integer := 18;

GPIO_WIDTH : integer := 37

);

PORT (

CLOCK_50 : IN STD_LOGIC;

UART_TXD : OUT STD_LOGIC;

-- Switches

SW : IN STD_LOGIC_VECTOR(SW_WIDTH-1 DOWNTO 0);

-- Push Buttons

KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

-- LEDs

LEDG : OUT STD_LOGIC_VECTOR(LEDG_WIDTH-1 DOWNTO 0);

LEDR : OUT STD_LOGIC_VECTOR(LEDR_WIDTH-1 DOWNTO 0);

GPIO : INOUT STD_LOGIC_VECTOR(GPIO_WIDTH-1 DOWNTO 0)

);

end UART_Top;

architecture Uart_tx_STRUCTURE of UART_Top is

-- UART Transmitter --

component TX is

port ( clk : IN STD_LOGIC;

Reset : IN STD_LOGIC;

Start : IN STD_LOGIC;

Baud_Rate : IN INTEGER;

Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

Done : OUT STD_LOGIC;

Running : OUT STD_LOGIC;

TX_Data : OUT STD_LOGIC);

end component TX;

-------------------------------------------------------------------------------------------

-- UART Test bench --

entity UART_TB is

end UART_TB;

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

USE ieee.numeric_std.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

use IEEE.math_real.all;

architecture Testing_UART of UART_TB is

-- TB constants --

constant LEDG_WIDTH : integer := 9;

constant LEDR_WIDTH : integer := 18;

constant SW_WIDTH : integer := 18;

constant GPIO_WIDTH : integer := 37;

----------------------------------

component UART_Top IS

generic (LEDG_WIDTH : integer := 9;

LEDR_WIDTH : integer := 18;

SW_WIDTH : integer := 18;

GPIO_WIDTH : integer := 37

);

PORT (

CLOCK_50: IN STD_LOGIC;

-- Switches

SW : IN STD_LOGIC_VECTOR(SW_WIDTH-1 DOWNTO 0);

-- Push Buttons

KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

-- LEDs

LEDG : OUT STD_LOGIC_VECTOR(LEDG_WIDTH-1 DOWNTO 0);

LEDR : OUT STD_LOGIC_VECTOR(LEDR_WIDTH-1 DOWNTO 0);

GPIO : INOUT STD_LOGIC_VECTOR(GPIO_WIDTH-1 DOWNTO 0)

);

end component;

------------------------------------------------------------------------------------------

-- gate sim TCL --

vcom -2008 UART_Top.vho
vsim -t ps -L work UART_TB
add wave -r /*
run -all
quit

---------------------------------------------------------

-- Error --

Errors: 0, Warnings: 0
# vsim -t ps -L work UART_TB
# vsim -t ps -L work UART_TB
# Start time: 10:17:46 on Aug 26,2025
# ** Note: (vsim-3812) Design is being optimized...
# ** Error (suppressible): C:/intelFPGA_lite/24.1std/quartus/qdesigns/HW_tested_verified_prjs/UART_TX_HW_test/UART_TB.vhd(56): (vopt-1271) Bad default binding for component instance "UUT: UART_Top".
# (Component generic "GPIO_WIDTH" is not on the entity "work.UART_Top".)
# (Entity is selected because it is in the same library as the design unit that contains the component.)
# Optimization failed
# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=2, Warnings=1.
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./gate_sim.do PAUSED at line 2

Fpga Devkit

RichardT_altera
3 months ago
Hi OP,

Hopefully, the example code provided in the github is sufficient as a reference to run the gate-level simulation successfully.

With that, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

The community users will be able to help you on your follow-up questions.

Thank you and have a great day!

Best Regards,

Richard Tan

7 Replies

AlanCLTan
Occasional Contributor
4 months ago
Hi,
The comparison of your component declaration in the testbench and the component declaration of UART_Top, one port is found missing:

UART_TXD : OUT STD_LOGIC;
Even though the error message complains about GPIO_WIDTH, the actual issue is likely due to incomplete port matching between the component and the entity.
Please check again.
Best regards,
Alan Tan
- Fpga_Egr_2025
  Occasional Contributor
  4 months ago
  Hi Alan,
  Thanks for pointing that out , i did corrected the UUT binding. But i am still getting the same error.
  I tried deleting the UART_Top.vho file , compiled the files again in quartus. Simulated again in RTL and then Gate level but Questasim is still stuck at this error .
  ---------------------------------------------------
  entity UART_TB is
  end UART_TB;
  
  LIBRARY ieee ;
  USE ieee.std_logic_1164.all ;
  USE ieee.numeric_std.all;
  use IEEE.std_logic_arith.all;
  use IEEE.std_logic_unsigned.all;
  use IEEE.math_real.all;
  
  architecture Testing_UART of UART_TB is
  
  -- TB constants --
  constant LEDG_WIDTH : integer := 9;
  constant LEDR_WIDTH : integer := 18;
  constant SW_WIDTH : integer := 18;
  constant GPIO_WIDTH : integer := 37;
  ----------------------------------
  
  component UART_Top IS
  
  generic (LEDG_WIDTH : integer := 9;
  LEDR_WIDTH : integer := 18;
  SW_WIDTH : integer := 18;
  GPIO_WIDTH : integer := 37
  );
  
  PORT (
  CLOCK_50 : IN STD_LOGIC;
  UART_TXD : OUT STD_LOGIC;
  -- Switches
  SW : IN STD_LOGIC_VECTOR(SW_WIDTH-1 DOWNTO 0);
  -- Push Buttons
  KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
  -- LEDs
  LEDG : OUT STD_LOGIC_VECTOR(LEDG_WIDTH-1 DOWNTO 0);
  LEDR : OUT STD_LOGIC_VECTOR(LEDR_WIDTH-1 DOWNTO 0);
  GPIO : INOUT STD_LOGIC_VECTOR(GPIO_WIDTH-1 DOWNTO 0)
  );
  end component;
  --
  signal Clock_50_tb, UART_TX_tb : STD_LOGIC;
  signal LEDR_tb, SW_tb : STD_LOGIC_VECTOR(SW_WIDTH-1 DOWNTO 0);
  signal LEDG_tb : STD_LOGIC_VECTOR(LEDG_WIDTH-1 DOWNTO 0);
  signal KEY_tb : STD_LOGIC_VECTOR(3 DOWNTO 0);
  signal GPIO_tb : STD_LOGIC_VECTOR(GPIO_WIDTH-1 DOWNTO 0);
  -------------------------------------------------------------------
  BEGIN
  
  -- instantiate the component under test
  UUT: UART_Top
  
  generic map( LEDG_WIDTH => LEDG_WIDTH,
  LEDR_WIDTH => LEDR_WIDTH,
  SW_WIDTH => SW_WIDTH,
  GPIO_WIDTH => GPIO_WIDTH
  )
  
  PORT MAP(
  CLOCK_50 => Clock_50_tb,
  UART_TXD => UART_TX_tb,
  SW => SW_tb,
  KEY => KEY_tb,
  LEDG => LEDG_tb,
  LEDR => LEDR_tb,
  GPIO => GPIO_tb
  );
  
  -----------------------------------------------------------------------
  --Questasim Error ------------------------
  # vsim -t ps -L work UART_TB
  # vsim -t ps -L work UART_TB
  # Start time: 17:36:29 on Aug 26,2025
  # ** Note: (vsim-3812) Design is being optimized...
  # ** Error (suppressible): C:/intelFPGA_lite/24.1std/quartus/qdesigns/HW_tested_verified_prjs/UART_TX_HW_test/UART_TB.vhd(58): (vopt-1271) Bad default binding for component instance "UUT: UART_Top".
  # (Component generic "GPIO_WIDTH" is not on the entity "work.UART_Top".)
  # (Entity is selected because it is in the same library as the design unit that contains the component.)
  # Optimization failed
  # ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=2, Warnings=1.
  # Error loading design
  # Error: Error loading design
  # Pausing macro execution
  # MACRO ./gate_sim.do PAUSED at line 2
  - Fpga_Egr_2025
    Occasional Contributor
    4 months ago
    Hi Alan,
    I modified the tb code as follows :
    
    entity UART_TB is
    end UART_TB;
    
    LIBRARY ieee ;
    USE ieee.std_logic_1164.all ;
    USE ieee.numeric_std.all;
    use IEEE.std_logic_arith.all;
    use IEEE.std_logic_unsigned.all;
    use IEEE.math_real.all;
    
    architecture Testing_UART of UART_TB is
    
    -- TB constants --
    constant LEDG_WIDTH : integer := 9;
    constant LEDR_WIDTH : integer := 18;
    constant SW_WIDTH : integer := 18;
    constant GPIO_WIDTH : integer := 37;
    ----------------------------------
    
    component UART_Top IS
    
    -- generic (LEDG_WIDTH : integer := 9;
    -- LEDR_WIDTH : integer := 18;
    -- SW_WIDTH : integer := 18;
    -- GPIO_WIDTH : integer := 37
    -- );
    
    PORT (
    CLOCK_50 : IN STD_LOGIC;
    UART_TXD : OUT STD_LOGIC;
    -- Switches
    SW : IN STD_LOGIC_VECTOR(SW_WIDTH-1 DOWNTO 0);
    -- Push Buttons
    KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    -- LEDs
    LEDG : OUT STD_LOGIC_VECTOR(LEDG_WIDTH-1 DOWNTO 0);
    LEDR : OUT STD_LOGIC_VECTOR(LEDR_WIDTH-1 DOWNTO 0);
    GPIO : INOUT STD_LOGIC_VECTOR(GPIO_WIDTH-1 DOWNTO 0)
    );
    end component;
    --
    signal Clock_50_tb, UART_TX_tb : STD_LOGIC;
    signal LEDR_tb, SW_tb : STD_LOGIC_VECTOR(SW_WIDTH-1 DOWNTO 0);
    signal LEDG_tb : STD_LOGIC_VECTOR(LEDG_WIDTH-1 DOWNTO 0);
    signal KEY_tb : STD_LOGIC_VECTOR(3 DOWNTO 0);
    signal GPIO_tb : STD_LOGIC_VECTOR(GPIO_WIDTH-1 DOWNTO 0);
    -------------------------------------------------------------------
    BEGIN
    
    -- instantiate the component under test
    UUT: UART_Top
    
    --generic map( LEDG_WIDTH => LEDG_WIDTH,
    -- LEDR_WIDTH => LEDR_WIDTH,
    -- SW_WIDTH => SW_WIDTH,
    -- GPIO_WIDTH => GPIO_WIDTH
    -- )
    
    PORT MAP(
    CLOCK_50 => Clock_50_tb,
    UART_TXD => UART_TX_tb,
    SW => SW_tb,
    KEY => KEY_tb,
    LEDG => LEDG_tb,
    LEDR => LEDR_tb,
    GPIO => GPIO_tb
    );
    ----------------------------------------------------------------------------
    ----------------------------------------------------------------------------
    --------- Questasim Error messages ------------------------------------
    vsim -t ps -L work UART_TB
    # vsim -t ps -L work UART_TB
    # Start time: 11:36:33 on Aug 27,2025
    # ** Note: (vsim-3812) Design is being optimized...
    # ** Error: C:/intelFPGA_lite/24.1std/quartus/qdesigns/HW_tested_verified_prjs/UART_TX_HW_test/UART_TB.vhd(58): (vopt-1134) Incompatible modes for port "UART_TXD" in component "UART_Top" when binding to entity "UART_Top".
    # ** Error: C:/intelFPGA_lite/24.1std/quartus/qdesigns/HW_tested_verified_prjs/UART_TX_HW_test/UART_TB.vhd(58): (vopt-1134) Incompatible modes for port "LEDG" in component "UART_Top" when binding to entity "UART_Top".
    # ** Error: C:/intelFPGA_lite/24.1std/quartus/qdesigns/HW_tested_verified_prjs/UART_TX_HW_test/UART_TB.vhd(58): (vopt-1134) Incompatible modes for port "LEDR" in component "UART_Top" when binding to entity "UART_Top".
    # ** Error: C:/intelFPGA_lite/24.1std/quartus/qdesigns/HW_tested_verified_prjs/UART_TX_HW_test/UART_TB.vhd(58): (vopt-1134) Incompatible modes for port "GPIO" in component "UART_Top" when binding to entity "UART_Top".
    # Optimization failed
    # ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=8, Warnings=1.
    # Error loading design
    # Error: Error loading design
    # Pausing macro execution
    # MACRO ./gate_sim.do PAUSED at line 2
    Now it is detecting incompatible modes for ports.
    Thanks,
    Regards
AlanCLTan
Occasional Contributor
4 months ago
Hi,
Could you try an experiments to see if it solves the error:
1. Remove the generic entity declaration, including GPIO_WIDTH, from the component declaration?
component UART_Top
port (
-- your ports here
);
end component;
----------------------------------
Remove the generic map from the instantiation?
UUT: UART_Top
port map(
-- your port mappings
);
----------------------------------
Best regards,
Alan Tan
RichardT_altera
Super Contributor
3 months ago
Thank you Alan for the answer.

I suspect there might be an issue with your design. You could try searching for publicly available UART designs for reference.
You may check out the webpage below, although the design is written in Verilog.
https://github.com/varmil/uart-verilog

I was able to simulate their design successfully.

Regards,
Richard Tan
- Fpga_Egr_2025
  Occasional Contributor
  3 months ago
  Hi Alan,
  Thanks for your reply , i have to stick to VHDL implementation i will search or modify the code .
  Thanks,
  Regards,
RichardT_altera
Super Contributor
3 months ago
Hi OP,

Hopefully, the example code provided in the github is sufficient as a reference to run the gate-level simulation successfully.

With that, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

The community users will be able to help you on your follow-up questions.

Thank you and have a great day!

Best Regards,

Richard Tan

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Gate Level Simulation

7 Replies

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