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Fpga_Egr_2025's avatar
Fpga_Egr_2025
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
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Gate Level Simulation

Hi , I am trying to run gate level simulation for my uart implementation, but for some reason the Questasim complains about UUT binding not correct . Although in RTL simulation it works fine. See b...
Fpga Devkit
  • RichardT_altera's avatar
    RichardT_altera
    11 months ago

    Hi OP,

    Hopefully, the example code provided in the github is sufficient as a reference to run the gate-level simulation successfully.

    With that, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

    The community users will be able to help you on your follow-up questions.

    Thank you and have a great day!

    Best Regards,

    Richard Tan

RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Thank you Alan for the answer.


I suspect there might be an issue with your design. You could try searching for publicly available UART designs for reference.

You may check out the webpage below, although the design is written in Verilog.

https://github.com/varmil/uart-verilog


I was able to simulate their design successfully.


Regards,

Richard Tan


  • Fpga_Egr_2025's avatar
    Fpga_Egr_2025
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Hi Alan,

    Thanks for your reply , i have to stick to VHDL implementation i will search or modify the code .

    Thanks,

    Regards,