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Fpga_Egr_2025's avatar
Fpga_Egr_2025
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

Gate Level Simulation

Hi , I am trying to run gate level simulation for my uart implementation, but for some reason the Questasim complains about UUT binding not correct . Although in RTL simulation it works fine. See b...
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  • RichardT_altera's avatar
    RichardT_altera
    11 months ago

    Hi OP,

    Hopefully, the example code provided in the github is sufficient as a reference to run the gate-level simulation successfully.

    With that, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

    The community users will be able to help you on your follow-up questions.

    Thank you and have a great day!

    Best Regards,

    Richard Tan

Fpga_Egr_2025's avatar
Fpga_Egr_2025
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hi Alan,

Thanks for pointing that out , i did corrected the UUT binding. But i am still getting the same error.

I tried deleting the UART_Top.vho file , compiled the files again in quartus. Simulated again in RTL and then Gate level but Questasim is still stuck at this error .

---------------------------------------------------

entity UART_TB is
end UART_TB;
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.numeric_std.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.math_real.all;
architecture Testing_UART of UART_TB is
-- TB constants --
constant LEDG_WIDTH : integer := 9;
constant LEDR_WIDTH : integer := 18;
constant SW_WIDTH : integer := 18;
constant GPIO_WIDTH : integer := 37;
----------------------------------
component UART_Top IS
generic (LEDG_WIDTH : integer := 9;
LEDR_WIDTH : integer := 18;
SW_WIDTH : integer := 18;
GPIO_WIDTH : integer := 37
);
PORT (
CLOCK_50 : IN STD_LOGIC;
UART_TXD : OUT STD_LOGIC;
-- Switches
SW : IN STD_LOGIC_VECTOR(SW_WIDTH-1 DOWNTO 0);
-- Push Buttons
KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-- LEDs
LEDG : OUT STD_LOGIC_VECTOR(LEDG_WIDTH-1 DOWNTO 0);
LEDR : OUT STD_LOGIC_VECTOR(LEDR_WIDTH-1 DOWNTO 0);
GPIO : INOUT STD_LOGIC_VECTOR(GPIO_WIDTH-1 DOWNTO 0)
);
end component;
--
signal Clock_50_tb, UART_TX_tb : STD_LOGIC;
signal LEDR_tb, SW_tb : STD_LOGIC_VECTOR(SW_WIDTH-1 DOWNTO 0);
signal LEDG_tb : STD_LOGIC_VECTOR(LEDG_WIDTH-1 DOWNTO 0);
signal KEY_tb : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal GPIO_tb : STD_LOGIC_VECTOR(GPIO_WIDTH-1 DOWNTO 0);
-------------------------------------------------------------------
BEGIN
-- instantiate the component under test
UUT: UART_Top
generic map( LEDG_WIDTH => LEDG_WIDTH,
LEDR_WIDTH => LEDR_WIDTH,
SW_WIDTH => SW_WIDTH,
GPIO_WIDTH => GPIO_WIDTH
)
PORT MAP(
CLOCK_50 => Clock_50_tb,
UART_TXD => UART_TX_tb,
SW => SW_tb,
KEY => KEY_tb,
LEDG => LEDG_tb,
LEDR => LEDR_tb,
GPIO => GPIO_tb
);
-----------------------------------------------------------------------
--Questasim Error ------------------------
# vsim -t ps -L work UART_TB
# vsim -t ps -L work UART_TB
# Start time: 17:36:29 on Aug 26,2025
# ** Note: (vsim-3812) Design is being optimized...
# ** Error (suppressible): C:/intelFPGA_lite/24.1std/quartus/qdesigns/HW_tested_verified_prjs/UART_TX_HW_test/UART_TB.vhd(58): (vopt-1271) Bad default binding for component instance "UUT: UART_Top".
# (Component generic "GPIO_WIDTH" is not on the entity "work.UART_Top".)
# (Entity is selected because it is in the same library as the design unit that contains the component.)
# Optimization failed
# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=2, Warnings=1.
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./gate_sim.do PAUSED at line 2
Fpga_Egr_2025's avatar
Fpga_Egr_2025
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hi Alan,

I modified the tb code as follows :

entity UART_TB is
end UART_TB;
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.numeric_std.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.math_real.all;
architecture Testing_UART of UART_TB is
-- TB constants --
constant LEDG_WIDTH : integer := 9;
constant LEDR_WIDTH : integer := 18;
constant SW_WIDTH : integer := 18;
constant GPIO_WIDTH : integer := 37;
----------------------------------
component UART_Top IS
-- generic (LEDG_WIDTH : integer := 9;
-- LEDR_WIDTH : integer := 18;
-- SW_WIDTH : integer := 18;
-- GPIO_WIDTH : integer := 37
-- );
PORT (
CLOCK_50 : IN STD_LOGIC;
UART_TXD : OUT STD_LOGIC;
-- Switches
SW : IN STD_LOGIC_VECTOR(SW_WIDTH-1 DOWNTO 0);
-- Push Buttons
KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-- LEDs
LEDG : OUT STD_LOGIC_VECTOR(LEDG_WIDTH-1 DOWNTO 0);
LEDR : OUT STD_LOGIC_VECTOR(LEDR_WIDTH-1 DOWNTO 0);
GPIO : INOUT STD_LOGIC_VECTOR(GPIO_WIDTH-1 DOWNTO 0)
);
end component;
--
signal Clock_50_tb, UART_TX_tb : STD_LOGIC;
signal LEDR_tb, SW_tb : STD_LOGIC_VECTOR(SW_WIDTH-1 DOWNTO 0);
signal LEDG_tb : STD_LOGIC_VECTOR(LEDG_WIDTH-1 DOWNTO 0);
signal KEY_tb : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal GPIO_tb : STD_LOGIC_VECTOR(GPIO_WIDTH-1 DOWNTO 0);
-------------------------------------------------------------------
BEGIN
-- instantiate the component under test
UUT: UART_Top
--generic map( LEDG_WIDTH => LEDG_WIDTH,
-- LEDR_WIDTH => LEDR_WIDTH,
-- SW_WIDTH => SW_WIDTH,
-- GPIO_WIDTH => GPIO_WIDTH
-- )
PORT MAP(
CLOCK_50 => Clock_50_tb,
UART_TXD => UART_TX_tb,
SW => SW_tb,
KEY => KEY_tb,
LEDG => LEDG_tb,
LEDR => LEDR_tb,
GPIO => GPIO_tb
);

----------------------------------------------------------------------------

----------------------------------------------------------------------------

--------- Questasim Error messages ------------------------------------

vsim -t ps -L work UART_TB
# vsim -t ps -L work UART_TB
# Start time: 11:36:33 on Aug 27,2025
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: C:/intelFPGA_lite/24.1std/quartus/qdesigns/HW_tested_verified_prjs/UART_TX_HW_test/UART_TB.vhd(58): (vopt-1134) Incompatible modes for port "UART_TXD" in component "UART_Top" when binding to entity "UART_Top".
# ** Error: C:/intelFPGA_lite/24.1std/quartus/qdesigns/HW_tested_verified_prjs/UART_TX_HW_test/UART_TB.vhd(58): (vopt-1134) Incompatible modes for port "LEDG" in component "UART_Top" when binding to entity "UART_Top".
# ** Error: C:/intelFPGA_lite/24.1std/quartus/qdesigns/HW_tested_verified_prjs/UART_TX_HW_test/UART_TB.vhd(58): (vopt-1134) Incompatible modes for port "LEDR" in component "UART_Top" when binding to entity "UART_Top".
# ** Error: C:/intelFPGA_lite/24.1std/quartus/qdesigns/HW_tested_verified_prjs/UART_TX_HW_test/UART_TB.vhd(58): (vopt-1134) Incompatible modes for port "GPIO" in component "UART_Top" when binding to entity "UART_Top".
# Optimization failed
# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=8, Warnings=1.
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./gate_sim.do PAUSED at line 2

Now it is detecting incompatible modes for ports.

Thanks,

Regards