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Fpga_Egr_2025's avatar
Fpga_Egr_2025
Icon for Occasional Contributor rankOccasional Contributor
6 months ago
Solved

Ashling RiscV NiosV errors

Hi I am trying to compile a simple hello world on NiosV targeting a CycloneIVE FPGA on DE2-115 board p/n : EP4CE115F29C7. But when i build project in Ashling RiscFree i get these errors which i dont ...
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BoonBengT_Altera's avatar
BoonBengT_Altera
Icon for Moderator rankModerator
6 months ago

Hi Fpga_Egr_2025,


Seems that there is a solution marked for your doubts. Hence would assume that your clarification has been answered, with no further clarification on this thread, it will be transitioned to community support for further help on doubts in this thread.


Please login to ‘ https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you for the questions and as always pleasure having you here.


Best Wishes

BB


Fpga_Egr_2025's avatar
Fpga_Egr_2025
Icon for Occasional Contributor rankOccasional Contributor
5 months ago

Hi , i was able to compile my design for the NiosV targeting CycloneIVE FPGA on DE2-115 board p/n : EP4CE115F29C7.

But now the JTAG debugging is not working, i searched the forums for that issue and it seems that clock speed has to be double of what system clock is i.e 50Mhz .

See screen shot attached.