YigalB1
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RESERVED_INPUT_WITH_WEAK_PULLUP pins in DE1- Lite
I would like to use 3 pins of the 40 pin connector of the DE10-Lite for UART implementation (Tx,Rx,GND). At first I was thinking of using V10 & V9 because they are top left on the connector, so easy to align. Yet they are far from the GND, so I am thinking now about W7 & V5, because they are near to the GND, so easy to use with 3 pins connector. However, the pinout table claims they are "RESERVED_INPUT_WITH_WEAK_PULLUP". Does it mean they can't be configured to be 3.3V input and output for the UART needs?Solved1.4KViews0likes4CommentsCan the NIOS be used outside the DE10 LIte?
A university project may use NIOS. This projects may want to tapeout later on. Can the NIOS, as configured, be used as Verilog RTL outside the DE10 Lite board for an actual tapeout? Is it possible technically? And even if yes, is there any legal limitation? Is it freeware?Solved910Views0likes3CommentsRe: How to instance SDRAM controller in DE10 Lite?
Thank you for the great positive attitude! However, VHDL is not my thing.... In the meantime I downloaded a Verilog model from GitHub. I compiled and simulated it and already found few bugs because the author probably made it work for a specific baud rate.... I am not sure why the internal seems so complicated to use with no documentation along with e many file it is using. I was expecting pure Verilog. I will search for documentation, yet it seems I will take your advise for using ready to go HDL, instead of the UART-RS232 IP.1.4KViews0likes0CommentsRe: How to instance SDRAM controller in DE10 Lite?
Thank you for clarifying. I was hoping to create some kind of automating a transfer of data from the host to the FPGA, few KB each time, and automatically getting back few bytes from the FPGA to the host, to allow usage of the FPGA as a tester: run a test based on the input data, and send back the results, so the host could compare expected vs actual results. Using the internal RAM could provide such a solution, but it seems no way to do this, but it looks like no way to do it. In this case implementing UART on the FPGA and using FTDI from the USB of the host to the GPIOs on the FPGA seems the only valid method. Is it? Thank you for answering.1.6KViews0likes5CommentsRe: DE10 Lite FPGA internal RAM usage
It seems I wrongly understood the answer above " It's only used as part of device programming or can be used for simulation.". In this case it seems I can't use the SDRAM as a means of data transfer between the host and the DE10 Lite. Thank you all for answering.844Views0likes0CommentsRe: DE10 Lite FPGA internal RAM usage
Ahh.. I start to understand: I noticed that programming the .sof is valid until power down, while .pof is much longer and "forever" (or next programming). Do you mean that the SDRAM is used to hold this .sof programming file until next power down? If so I may have another approach: 1- I assume this data can be overwritten after the FPGA was programmed, so it is not needed after that moment. 2- What portion of the SDRAM is used for the FPGA? 3- Is it possible to manipulate the .sof file, and fill it with my data, following the FPGA programming required? 4- Is it possible to manipulate the programming process in this way: send the data to the SDRAM as if it is going to be programmed, but not program the FPGA? If so, the process can be: a) program the FPGA with .pof file (One time, long). b) Send manipulated .sof file, which will not be programmed, and then the FPGA will be able to use this content for processing the SDRAM content. 5- What is the process on the DE10 Lite after the SDRAM was programmed with .sof file? Where is the programming logic residing? How is it triggered after the .sof file is written to the FPGA? (is there a documentation for that?)913Views0likes2CommentsRe: How to instance SDRAM controller in DE10 Lite?
Yes, I mean instantiating it, and I think I made a mistake: it is probably DDR3 and not DDR4. Here is what I see in the IP catalog: I am not sure why PHY is required if this is on board FPGA and connected directly to the FPGA with control signals. I think this IP is not intended for the onboard DDR chip. Still, assuming there is no SDRAM IP, such a controller can be placed inside the FPGA. Is there a way to program the SDRAM from the host directly, without using the SDRAM controller on the FPGA? The target is to use the SDRAM as a large buffer, filling it with data from the host, and then letting the FPGA process this data.1.6KViews0likes1Comment
