Forum Discussion
New ContributorHow to instance SDRAM controller in DE10 Lite?
- Clearly ease of use. Works without installing JTAG stack (at least Standalone-Programmer) on the client computer.
Altera/Intel RS232 UART IP uses AVMM interface which I don't need in basic HDL debug logic design. I have simple Rx and Tx code with fixed baudrate (921k) written from the scratch. There's no code I can send you as is, I'll check if I can extract something. There are however tons of UART code on the net.
New ContributorThank you for clarifying. I was hoping to create some kind of automating a transfer of data from the host to the FPGA, few KB each time, and automatically getting back few bytes from the FPGA to the host, to allow usage of the FPGA as a tester: run a test based on the input data, and send back the results, so the host could compare expected vs actual results.
Using the internal RAM could provide such a solution, but it seems no way to do this, but it looks like no way to do it.
In this case implementing UART on the FPGA and using FTDI from the USB of the host to the GPIOs on the FPGA seems the only valid method. Is it?
Thank you for answering.
FvMSuper Contributor
I have test applications communicating with FPGA through JTAG and debug IP (Source&Probe and In-System Memory Content Editor). That's definitely possible. Nevertheless I switched to UART interface with newer designs.- YigalB1
1) Why did you switch to UART? Performance? Ease of use?
2) What UART did you use? The "RS232 UART" from the IP catalog?
3) can you share your code for both options?
- FvMClearly ease of use. Works without installing JTAG stack (at least Standalone-Programmer) on the client computer.
Altera/Intel RS232 UART IP uses AVMM interface which I don't need in basic HDL debug logic design. I have simple Rx and Tx code with fixed baudrate (921k) written from the scratch. There's no code I can send you as is, I'll check if I can extract something. There are however tons of UART code on the net.
