YigalB1
New Contributor
New ContributorRESERVED_INPUT_WITH_WEAK_PULLUP pins in DE1- Lite
I would like to use 3 pins of the 40 pin connector of the DE10-Lite for UART implementation (Tx,Rx,GND). At first I was thinking of using V10 & V9 because they are top left on the connector, so easy...
Hi,
according to DE10-Lite schematic, all GPIO connector pins are connected to RX/TX capable pins in 3.3V IO banks, also questioned GPIO_7 and GPIO_9. I presume, you are seeing "RESERVED_INPUT_WITH_WEAK_PULLUP" in the .pin file of a specific project. It reflects the pin assignments of the design, not the capabilities of the FPGA. "Reserved input" is the assignment of an unused pin. You need to assign intended pins to top level signals in Pin Planner tool or Assignment Editor.
