admaris
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Agilex FPGA PRBS Testing Issue
I want to use the Agilex-AGIB027R29A1e1VB-FPGA-REVC-V24.3.1b89-V1.0 project in the examples/qsfpdd_nrz directory to test two groups of Ethernet interfaces for PRBS and count the test results. But after compiling the project and burning it into the board, when I open the system console and load the .sof file, I don’t know how to proceed. Here’s what I see: I’ve opened two collections. In collection_1, the channel status is active. But when I click TX start, clicking RX start doesn’t do anything. In collection_2, the channel status is unknown, and I don’t know how to make it active. I think this might be related to the toolkit parameters. Can you provide detailed steps to help me achieve my goal?Re: 'New Nios II Application and BSP from template' Freezing and Unresponsiveness in Eclipse
I ran the command <quartus_install_path>/nios2eds/nios2_command_shell.sh, and after reopening the "Nios II Software Build Tools for Eclipse" from Quartus, I noticed that the Eclipse interface had reverted to an older version. However, when I ran my project again, it no longer hung. I'm not quite sure why running this command resolved the issue, but it worked.'New Nios II Application and BSP from template' Freezing and Unresponsiveness in Eclipse
I have created a Nios II Qsys project in Quartus Std 23.1, and I'm encountering two different issues with Eclipse. 1. When I try to use 'New Nios II Application and BSP from template,' there is no response at all. The action seems to have no effect. 2. On rare occasions, when I do get the 'New Nios II Application and BSP from template' wizard to open and move to the next step, after selecting the .sopcinfo file from my project, the interface freezes and does not proceed further. Could you please help identify the potential causes of these issues and suggest a solution?'New Nios II Application and BSP from template' Freezing and Unresponsiveness in Eclipse
I have created a Nios II Qsys project in Quartus Std 23.1, and I'm encountering two different issues with Eclipse. 1. When I try to use 'New Nios II Application and BSP from template,' there is no response at all. The action seems to have no effect. 2. On rare occasions, when I do get the 'New Nios II Application and BSP from template' wizard to open and move to the next step, after selecting the .sopcinfo file from my project, the interface freezes and does not proceed further. Could you please help identify the potential causes of these issues and suggest a solution?Inquiry Regarding I/O PLL Configuration and Output Clock Issues on Agilex 7 M FPGA
Dear Intel Technical Support, I am currently working with the Agilex 7 M series FPGA and using the I/O PLL Intel FPGA IP core in my design. I have encountered a couple of issues that I need your assistance with: 1、I/O PLL Desired Output Frequency Change Not Reflected: After modifying the outclk0 parameter (desired frequency) in the I/O PLL IP core and recompiling the project, I noticed that the output clock in the timing analyzer still shows the previous value, not the updated one. I came across a recommendation in the IP manual stating that Intel recommends compiling the I/O PLL designs with each intended configuration setting to determine the variation in the clock with the I/O PLL settings. Could you please clarify where exactly I should implement these configuration settings to ensure that the desired output frequency change is correctly reflected in the timing analyzer? 2、Using a Single Oscillator with Multiple Output Frequencies: In my design, I am using a single oscillator as the input clock source for the I/O PLL and generating multiple different output frequencies. However, my design is not working as expected. Is this approach valid, or could there be an issue with how the I/O PLL IP core is configured when using a single clock source for multiple output clocks? Are there any specific guidelines or constraints I should follow for such configurations? I would greatly appreciate your assistance in resolving these issues. Thank you for your time and support.Clarification on HBM Capacity and AXI4 Interface for Agilex 7 M Series
Dear Intel Technical Support, I have a question regarding the Agilex 7 M series FPGA, specifically related to the HBM (High Bandwidth Memory) configuration. 1、The maximum HBM capacity for the Agilex 7 M series is 32GB, but the NOC initiator AXI4 user interface has an address width of 44 bits. Given that 32GB should theoretically require only a 35-bit address width, I would like to understand why a 44-bit address width is used. Could you provide insight into the reasoning behind this? 2、Additionally, when reading and writing data in 512-bit chunks, is there any specific requirement regarding the user-side clock frequency? Specifically, is there a minimum or maximum frequency that the user-side clock must support, or can it be lowered to a specific frequency? Thank you for your assistance, and I look forward to your response. Best regards,Inquiry About Compatibility of Multi Channel DMA IP Driver with Agilex 7 M-Series Board
I am currently working with an Agilex 7 M-Series development board, specifically the AGMF039R47A1E2VR0 model, for FPGA development. In my project, I plan to use PCIe DMA to transfer data to the HBM and have selected the Multi Channel DMA Intel® FPGA IP for PCI Express for this purpose. After reviewing the example design documentation and the User Guide, I have a few questions that I hope you can help address: Driver Compatibility: The example design uses the active serial ×4 interface and provides a corresponding driver. However, the board I am using is configured with the AVST ×8 interface. Could you confirm if the provided driver in the example design supports the AVST ×8 interface? If not, are there any recommended development steps or alternative solutions for compatibility? Hardware Support: In the "Device Hardware Requirements" section of the example design User Guide, I noticed that the AGMF039R47A1E2VR0 model is not listed as a supported device. Could you confirm whether this board is compatible with the Multi Channel DMA IP? If not, are there any recommended alternatives or solutions? Additional Resources: Are there any specific drivers or reference designs available for the AGMF039R47A1E2VR0 board that could help with my use case? I look forward to your response.Re: simulation for the HBM2E Interface FPGA IP
Hi Thank you for your reply. The kernel is as follows: Linux legion-desktop 5.15.0-122-generic #132~20.04.1-Ubuntu SMP Fri Aug 30 15:50:07 UTC 2024 x86_64 x86_64 x86_64 GNU/Linux I tried to launch Questasim with the command "vsim -nocvg &" and changed the setup script, which is the same as what you used. The EMIF IP example design is directly retrieved from the IP library. I printed the output of running HBM2e into the info.log file below. Thank you~
