Inquiry Regarding I/O PLL Configuration and Output Clock Issues on Agilex 7 M FPGA

Dear Intel Technical Support, I am currently working with the Agilex 7 M series FPGA and using the I/O PLL Intel FPGA IP core in my design. I have encountered a couple of issues that I need your assistance with: 1、I/O PLL Desired Output Frequency Change Not Reflected: After modifying the outclk0 parameter (desired frequency) in the I/O PLL IP core and recompiling the project, I noticed that the output clock in the timing analyzer still shows the previous value, not the updated one. I came across a recommendation in the IP manual stating that Intel recommends compiling the I/O PLL designs with each intended configuration setting to determine the variation in the clock with the I/O PLL settings. Could you please clarify where exactly I should implement these configuration settings to ensure that the desired output frequency change is correctly reflected in the timing analyzer? 2、Using a Single Oscillator with Multiple Output Frequencies: In my design, I am using a single oscillator as the input clock source for the I/O PLL and generating multiple different output frequencies. However, my design is not working as expected. Is this approach valid, or could there be an issue with how the I/O PLL IP core is configured when using a single clock source for multiple output clocks? Are there any specific guidelines or constraints I should follow for such configurations? I would greatly appreciate your assistance in resolving these issues. Thank you for your time and support.