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admaris's avatar
admaris
Icon for New Contributor rankNew Contributor
1 year ago

Inquiry Regarding I/O PLL Configuration and Output Clock Issues on Agilex 7 M FPGA

Dear Intel Technical Support, I am currently working with the Agilex 7 M series FPGA and using the I/O PLL Intel FPGA IP core in my design. I have encountered a couple of issues that I need your assis...
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AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi,


Thank you for contacting us in this community forum.

Are you willing to share your design for me to look into?

If yes, you can archive your design and share the .qar file through email. I will initiate the email.


Regards,

Aqid