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admaris's avatar
admaris
Icon for New Contributor rankNew Contributor
1 year ago

Inquiry Regarding I/O PLL Configuration and Output Clock Issues on Agilex 7 M FPGA

Dear Intel Technical Support, I am currently working with the Agilex 7 M series FPGA and using the I/O PLL Intel FPGA IP core in my design. I have encountered a couple of issues that I need your assis...
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AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.