SimonT
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Re: NIOS V Sysnthesis Fails with Quartus 25.1 Lite
The .qsys file was created completly from scratch with Platfrom Designer 25.1. There are some standard warnings, but nothing unexpected. Warning: niosv.intel_niosv_m_0: Properties (associatedClock) have been set on interface reset - in composed mode these are ignored Warning: niosv.intel_niosv_m_0: Properties (associatedClock,associatedReset) have been set on interface instruction_manager - in composed mode these are ignored Warning: niosv.intel_niosv_m_0: Properties (associatedClock,associatedReset) have been set on interface data_manager - in composed mode these are ignored Warning: niosv.intel_niosv_m_0: Properties (associatedClock) have been set on interface reset - in composed mode these are ignored Warning: niosv.intel_niosv_m_0: Properties (associatedClock,associatedReset) have been set on interface instruction_manager - in composed mode these are ignored Warning: niosv.intel_niosv_m_0: Properties (associatedClock,associatedReset) have been set on interface data_manager - in composed mode these are ignoredNIOS V Sysnthesis Fails with Quartus 25.1 Lite
Hi, I used Quartus 23.1 Lite for a couple of months and have now switched to Quartus 25.1 Lite. Since the version update my NIOS V Plattform Designer Projects do not synthesize any longer. Synthesis fails with: Info (12128): Elaborating entity "niosv" for hierarchy "niosv:u0" Info (12128): Elaborating entity "niosv_intel_niosv_m_0" for hierarchy "niosv:u0|niosv_intel_niosv_m_0:intel_niosv_m_0" Info (12128): Elaborating entity "niosv_intel_niosv_m_0_hart" for hierarchy "niosv:u0|niosv_intel_niosv_m_0:intel_niosv_m_0|niosv_intel_niosv_m_0_hart:hart" Error (10835): SystemVerilog error at riscv.pkg.sv(149): no support for unions Error (10835): SystemVerilog error at riscv.pkg.sv(333): no support for unions Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1163): encoded value for element "MXL32" has width 32, which does not match the width of the enumeration's base type (2) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1164): encoded value for element "MXL64" has width 32, which does not match the width of the enumeration's base type (2) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1165): encoded value for element "MXL128" has width 32, which does not match the width of the enumeration's base type (2) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1167): encoded value for element "MXL_RESERVED" has width 32, which does not match the width of the enumeration's base type (2) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1233): encoded value for element "INSTRUCTION_MISALIGNED" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1234): encoded value for element "INSTRUCTION_ACCESS_FAULT" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1235): encoded value for element "ILLEGAL_INSTRUCTION" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1236): encoded value for element "BREAKPOINT" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1237): encoded value for element "LOAD_ADDRESS_MISALIGNED" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1238): encoded value for element "LOAD_ACCESS_FAULT" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1239): encoded value for element "STORE_AMO_ADDRESS_MISALIGNED" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1240): encoded value for element "STORE_AMO_ACCESS_FAULT" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1241): encoded value for element "USER_ECALL" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1242): encoded value for element "SUPERVISOR_ECALL" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1243): encoded value for element "MACHINE_ECALL" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1244): encoded value for element "INSTRUCTION_PAGE_FAULT" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1245): encoded value for element "LOAD_PAGE_FAULT" has width 32, which does not match the width of the enumeration's base type (5) Error (12152): Can't elaborate user hierarchy "niosv:u0|niosv_intel_niosv_m_0:intel_niosv_m_0|niosv_intel_niosv_m_0_hart:hart" Info (144001): Generated suppressed messages file /home/simon/Documents/QuartusPrime/MAX10_InternalFlash_Ticket/output_files/MAX10_InternalFlash_Ticket.map.smsg Error: Quartus Prime Analysis & Synthesis was unsuccessful. 20 errors, 30 warnings Error: Peak virtual memory: 369 megabytes Error: Processing ended: Mon Nov 10 09:24:51 2025 Error: Elapsed time: 00:00:39 Error: Total CPU time (on all processors): 00:01:41 Error (293001): Quartus Prime Full Compilation was unsuccessful. 22 errors, 30 warnings I am using the DE10-Lite Board with the Golden Top example Design and add a very basic Nios V to it. //======================================================= // Structural coding //======================================================= niosv u0 ( .clk_clk (MAX10_CLK1_50), // clk.clk .reset_reset_n (1'b1) // reset.reset_n ); Any idead how I can fix that Issue? Best regards SimonCreate a device driver for a composed component
I have created a composed component that includes multiple avalon components. e.g. one altera_avalon_spi and 2 altera_avalon_pio instances. With platform designer I have exported the system as _hw.tcl file. Additionaly I have created a _sw.tcl file to define a device driver for the composed component. The composed component is included in a parent NiosV QSYS system. Now I want to create the BSP for this system. My goal is to have a single driver for the composed component. From that single driver I want to control the SPI and PIO instances whithin that composed component and their interaction. The problem is, that within the BSP editor the component instances that are defined in the composed component are still completly independent. Also the sw driver defined in the _sw.tcl is not available in the BSP Editor. How can I create a single driver for a composed component?Re: Building a composed component with a instance that has a SYSTEM_INFO parameter
Thanks Richard. I did not knew that it is possible to create the _hw.tcl directly from platform designer. That is brilliant and simplify things a lot. I have now successfully created a composed with one altera_avalon_spi and 2 altera_avalon_pio instances and called it myCircuit_hw.tcl Additionally I have created a myCircuit_sw.tcl for the component. The component is integrated in a parent qsys file with niosv processor and compiles. When I generate the BSP the, BSP editor shows three Modules, but not the driver defined in the myCircuit_sw.tcl All three modules have some dependecy. Therefore I want to not only link them in HW, but also have a single SW driver, that handles the communication with the SPI and both PIOs.Building a composed component with a instance that has a SYSTEM_INFO parameter
I have an integrated circuit connected to the FPGA. The circuit has an SPI interface and various other interfaces. For portablity of my HDL and SW code I want to use platform designer and build a composed component with a SW driver to control the device in various applications. For initial testing I startet with a simple _hw.tcl file wich includes only the SPI master and exports all it's interfaces. package require -exact qsys 16.1 set_module_property name my_composed_component set_module_property COMPOSITION_CALLBACK composed_component proc composed_component {} { # Instances add_instance spiInstance altera_avalon_spi # add_instance myComponent_A; To be added later # add_instance myComponent_B; To be added later # Interfaces add_interface clk clock end add_interface reset reset end add_interface spi_control_port avalon slave add_interface spi_irq interrupt end add_interface external conduit end # Connections set_interface_property clk EXPORT_OF spiInstance.clk set_interface_property reset EXPORT_OF spiInstance.reset set_interface_property spi_control_port EXPORT_OF spiInstance.spi_control_port set_interface_property spi_irq EXPORT_OF spiInstance.irq set_interface_property external EXPORT_OF spiInstance.external } Including the component in Platform designer works perfectly fine, but I am not able to generate the HDL code. During generation the following errors pop up. Info: spiInstance: Starting RTL generation for module 'niosv_my_composed_component_0_spiInstance' Info: spiInstance: Generation command is [exec /home/simon/intelFPGA_lite/23.1std/quartus/linux64/perl/bin/perl -I /home/simon/intelFPGA_lite/23.1std/quartus/linux64/perl/lib -I /home/simon/intelFPGA_lite/23.1std/quartus/sopc_builder/bin/europa -I /home/simon/intelFPGA_lite/23.1std/quartus/sopc_builder/bin -I /home/simon/intelFPGA_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/common -I /home/simon/intelFPGA_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_spi -- /home/simon/intelFPGA_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_spi/generate_rtl.pl --name=niosv_my_composed_component_0_spiInstance --dir=/tmp/alt0333_2429507840219227742.dir/0008_spiInstance_gen/ --quartus_dir=/home/simon/intelFPGA_lite/23.1std/quartus --verilog --config=/tmp/alt0333_2429507840219227742.dir/0008_spiInstance_gen//niosv_my_composed_component_0_spiInstance_component_configuration.pl --do_build_sim=0 ] Info: spiInstance: Illegal division by zero at /home/simon/intelFPGA_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_spi/em_spi_qsys.pm line 330. Info: spiInstance: Done RTL generation for module 'niosv_my_composed_component_0_spiInstance' Error: spiInstance: Failed to find module niosv_my_composed_component_0_spiInstance Info: spiInstance: "my_composed_component_0" instantiated altera_avalon_spi "spiInstance" Error: Generation stopped, 108 or more modules remaining Info: niosv: Done "niosv" with 40 modules, 16 files Error: qsys-generate failed with exit code 1: 2 Errors, 3 Warnings I think the problem that the spi instance is not found results from Info: spiInstance: Illegal division by zero at /home/simon/intelFPGA_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_spi/em_spi_qsys.pm line 330. I have checked the content of the PM file. In line 330 the following code is executed my $ss_delay_quantum = $CLOCKDIV / $clock_freq / 2; The clock frequency is a SYSTEM_INFO based parameter add_parameter inputClockRate LONG set_parameter_property inputClockRate DEFAULT_VALUE {0} set_parameter_property inputClockRate DISPLAY_NAME {inputClockRate} set_parameter_property inputClockRate VISIBLE {0} set_parameter_property inputClockRate AFFECTS_GENERATION {1} set_parameter_property inputClockRate HDL_PARAMETER {0} set_parameter_property inputClockRate SYSTEM_INFO {clock_rate clk} set_parameter_property inputClockRate SYSTEM_INFO_TYPE {CLOCK_RATE} set_parameter_property inputClockRate SYSTEM_INFO_ARG {clk} It seems that the clock frequency is not set correct and remains at it's default value 0. After a bit of research I have found another ticket with a very similar issue. Also in this case there is an issue with a component instance that makes use of a SYSTEM_INFO parameter. https://community.intel.com/t5/Intel-Quartus-Prime-Software/How-to-get-QSYS-to-propagate-SYSTEM-INFO-GENERATION-ID-value/m-p/1365929 I think that the issue I am observing here is a bug. It seems that it is simply impossible to use component instances that relay on SYSTEM_INFO parameters within a composed component. Is there any way to use instances with SYSTEM_INFO parameter within a composed component? If not, is there any other method to create a custom component that includes multiple component instances and can be linked to a single _sw.tcl driver? Version Information: Quartus Prime Lite 23.1
