SimonT
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Realistic values for set_max_skew
I have a design with asynchronous input and output bus signals. For the input bus signals I do not care how much time it takes from the Input Ports to the first register. For the output signals I also do not care how much time it takes from the last register to the output ports. The only thing that I really care about is, the skew of the bus signals. I have created a very simple dummy design and added sdc design constraints. module top( input clk, input [1:0] input_bus, output reg [1:0] output_bus ); reg [1:0] register; always @(posedge clk) begin register <= input_bus; output_bus <= register; end endmodule create_clock -name clk -period 20 [get_ports clk] set_max_skew -from [get_ports {input_bus[*]}] 0.5 set_max_skew -to [get_ports {output_bus[*]}] 0.5 Timing Analyzer fails. I do not have a lot of experience with SDC constraints and bus timing. My feelfing is, that 0.5ns bus skew is not unrealistic. Is my expectation wrong, or am I doing something wrong?Re: DE10-Lite and sdram controller ip
Hi, I had the same Issue. For me the Eval Kit was quite useless without that IP core. I found the following temporary "solution" in https://community.altera.com/discussions/ip-and-transceiver/replacement-for-sdram-controller-after-v16-1/52218 Copy the IP core from an Old Quartus ( I think the last version where this core was supported is 18.1) version to the new Quartus version. /ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller Additionally you need to modify the ip/altera/altera_component.ipx file. You have to add a few additional lines to that file. </plugin> <component name="altera_avalon_new_sdram_controller" file="sopc_builder_ip/altera_avalon_new_sdram_controller/altera_avalon_new_sdram_controller_hw.tcl" displayName="SDRAM Controller Intel FPGA IP" version="20.1" description="" tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=false" categories="Memory Interfaces and Controllers/SDRAM" factory="TclModuleFactory"> <tag2 key="COMPONENT_EDITABLE" value="false" /> <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" /> <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" /> <tag2 key="ELABORATION_CALLBACK" value="elaborate" /> <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" /> <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" /> <tag2 key="TCL_PACKAGE_VERSION" value="12.0" /> <tag2 key="VALIDATION_CALLBACK" value="validate" /> <documentUrl displayName="User Guide" type="OTHER" url="https://documentation.altera.com/#/link/sfo1400787952932/iga1401314928585" /> <documentUrl displayName="Release Notes" type="OTHER" url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697689300" /> </component> <plugin name="altera_avalon_new_sdram_controller.qprs" file="sopc_builder_ip/altera_avalon_new_sdram_controller/altera_avalon_new_sdram_controller.qprs" displayName="altera_avalon_new_sdram_controller.qprs" version="0.0" description="" tags="" categories="" type="com.altera.sopcmodel.util.IElementPresetList" subtype="" factory="PresetFactory"> <tag2 key="PRESET_TYPE" value="altera_avalon_new_sdram_controller" /> </plugin> These entries are taken from the old altera_component.ipx This worked for me in Quartus 23.1 LiteRe: NIOS V Sysnthesis Fails with Quartus 25.1 Lite
The .qsys file was created completly from scratch with Platfrom Designer 25.1. There are some standard warnings, but nothing unexpected. Warning: niosv.intel_niosv_m_0: Properties (associatedClock) have been set on interface reset - in composed mode these are ignored Warning: niosv.intel_niosv_m_0: Properties (associatedClock,associatedReset) have been set on interface instruction_manager - in composed mode these are ignored Warning: niosv.intel_niosv_m_0: Properties (associatedClock,associatedReset) have been set on interface data_manager - in composed mode these are ignored Warning: niosv.intel_niosv_m_0: Properties (associatedClock) have been set on interface reset - in composed mode these are ignored Warning: niosv.intel_niosv_m_0: Properties (associatedClock,associatedReset) have been set on interface instruction_manager - in composed mode these are ignored Warning: niosv.intel_niosv_m_0: Properties (associatedClock,associatedReset) have been set on interface data_manager - in composed mode these are ignoredNIOS V Sysnthesis Fails with Quartus 25.1 Lite
Hi, I used Quartus 23.1 Lite for a couple of months and have now switched to Quartus 25.1 Lite. Since the version update my NIOS V Plattform Designer Projects do not synthesize any longer. Synthesis fails with: Info (12128): Elaborating entity "niosv" for hierarchy "niosv:u0" Info (12128): Elaborating entity "niosv_intel_niosv_m_0" for hierarchy "niosv:u0|niosv_intel_niosv_m_0:intel_niosv_m_0" Info (12128): Elaborating entity "niosv_intel_niosv_m_0_hart" for hierarchy "niosv:u0|niosv_intel_niosv_m_0:intel_niosv_m_0|niosv_intel_niosv_m_0_hart:hart" Error (10835): SystemVerilog error at riscv.pkg.sv(149): no support for unions Error (10835): SystemVerilog error at riscv.pkg.sv(333): no support for unions Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1163): encoded value for element "MXL32" has width 32, which does not match the width of the enumeration's base type (2) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1164): encoded value for element "MXL64" has width 32, which does not match the width of the enumeration's base type (2) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1165): encoded value for element "MXL128" has width 32, which does not match the width of the enumeration's base type (2) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1167): encoded value for element "MXL_RESERVED" has width 32, which does not match the width of the enumeration's base type (2) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1233): encoded value for element "INSTRUCTION_MISALIGNED" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1234): encoded value for element "INSTRUCTION_ACCESS_FAULT" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1235): encoded value for element "ILLEGAL_INSTRUCTION" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1236): encoded value for element "BREAKPOINT" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1237): encoded value for element "LOAD_ADDRESS_MISALIGNED" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1238): encoded value for element "LOAD_ACCESS_FAULT" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1239): encoded value for element "STORE_AMO_ADDRESS_MISALIGNED" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1240): encoded value for element "STORE_AMO_ACCESS_FAULT" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1241): encoded value for element "USER_ECALL" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1242): encoded value for element "SUPERVISOR_ECALL" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1243): encoded value for element "MACHINE_ECALL" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1244): encoded value for element "INSTRUCTION_PAGE_FAULT" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1245): encoded value for element "LOAD_PAGE_FAULT" has width 32, which does not match the width of the enumeration's base type (5) Error (12152): Can't elaborate user hierarchy "niosv:u0|niosv_intel_niosv_m_0:intel_niosv_m_0|niosv_intel_niosv_m_0_hart:hart" Info (144001): Generated suppressed messages file /home/simon/Documents/QuartusPrime/MAX10_InternalFlash_Ticket/output_files/MAX10_InternalFlash_Ticket.map.smsg Error: Quartus Prime Analysis & Synthesis was unsuccessful. 20 errors, 30 warnings Error: Peak virtual memory: 369 megabytes Error: Processing ended: Mon Nov 10 09:24:51 2025 Error: Elapsed time: 00:00:39 Error: Total CPU time (on all processors): 00:01:41 Error (293001): Quartus Prime Full Compilation was unsuccessful. 22 errors, 30 warnings I am using the DE10-Lite Board with the Golden Top example Design and add a very basic Nios V to it. //======================================================= // Structural coding //======================================================= niosv u0 ( .clk_clk (MAX10_CLK1_50), // clk.clk .reset_reset_n (1'b1) // reset.reset_n ); Any idead how I can fix that Issue? Best regards SimonCreate a device driver for a composed component
I have created a composed component that includes multiple avalon components. e.g. one altera_avalon_spi and 2 altera_avalon_pio instances. With platform designer I have exported the system as _hw.tcl file. Additionaly I have created a _sw.tcl file to define a device driver for the composed component. The composed component is included in a parent NiosV QSYS system. Now I want to create the BSP for this system. My goal is to have a single driver for the composed component. From that single driver I want to control the SPI and PIO instances whithin that composed component and their interaction. The problem is, that within the BSP editor the component instances that are defined in the composed component are still completly independent. Also the sw driver defined in the _sw.tcl is not available in the BSP Editor. How can I create a single driver for a composed component?Re: Building a composed component with a instance that has a SYSTEM_INFO parameter
Thanks Richard. I did not knew that it is possible to create the _hw.tcl directly from platform designer. That is brilliant and simplify things a lot. I have now successfully created a composed with one altera_avalon_spi and 2 altera_avalon_pio instances and called it myCircuit_hw.tcl Additionally I have created a myCircuit_sw.tcl for the component. The component is integrated in a parent qsys file with niosv processor and compiles. When I generate the BSP the, BSP editor shows three Modules, but not the driver defined in the myCircuit_sw.tcl All three modules have some dependecy. Therefore I want to not only link them in HW, but also have a single SW driver, that handles the communication with the SPI and both PIOs.
