KRoma6
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Clocking with Cyclone 10 Hard IP for PCIe, NIOS II processors, and mSGDMA.
I have a project with several IP blocks in platform designer: Cyclone 10 Hard IP for PCIe, NIOS II, mSGDMA, emif, onchip memory, IOPLL, and LVDS. In Intel's example design for Hard IP for PCIe express, all clock inputs run off the "coreclkout_hip" of the PCIe hard IP. In this design if use the "coreclkout_hip" to run NIOS II process and mSGDMA it will not pass timing requirements. I've tried passing the clock through a buffer but get the same results. What are clocking strategies for using multiple IP blocks with Hard IP for PCIe? Thanks, -KyleClocking with Cyclone 10 Hard IP for PCIe, NIOS II processors, and mSGDMA.
I have a project with several IP blocks in platform designer: Cyclone 10 Hard IP for PCIe, NIOS II, mSGDMA, emif, onchip memory, IOPLL, and LVDS. In Intel's example design for Hard IP for PCIe express, all clock inputs run off the "coreclkout_hip" of the PCIe hard IP. In this design if use the "coreclkout_hip" to run NIOS II process and mSGDMA it will not pass timing requirements. I've tried passing the clock through a buffer but get the same results. What are clocking strategies for using multiple IP blocks with Hard IP for PCIe? Thanks, -KyleRe: Cyclone 10 GX 40GBASE support
Hello, Thanks for the reply. So there is support for the 40GBASE PHY but not the MAC? Do you no of any third party MAC IP providers? We already have the board design finished for the Cyclone. Can the Arria IP be leveraged for us to create our own MAC or will this have to be done from scratch? Thanks, -KCyclone 10 GX 40GBASE support
Hello, I am designing a 40GBASE application with the Cyclone 10 GX. The XCVR transceiver user guide gives limited direction to setting up the platform designer with this protocol. First, is there a 40GBASE MAC IP for this card? I am assuming you cannot configure four 10GBASE MAC IP to implement 40GBASE. Second, how is the Enhanced PCS interface width determined? Third, are there any other specific setting in the Native PHY, reset controller, or PLL to implement 40GBASE? Fourth, does the reset controller need to be with the same clock as the PHY and PLL? Finally, is there an example design I can take a look at? Thanks, -KDriver Code for DMA with PCIe Hard IP on Cyclone 10 GX dev board
Hello, I am looking for a driver code example for read/writes through DMA with PCIe Hard IP on Cyclone 10 GX. I am following the user guide on programming the configuration registers and setting up descriptor tables but my computer freezes every time I run it. I am using the design example for Cyclone 10 GX PCIe Hard IP with DMA using the Cyclone 10 GX dev board. Looking for open source driver code or a similar example. Thanks,mSGDMA to LVDS SERDES
What is the best way to send data to and from memory / LVDS SERDES? I currently have a mSGDMA (MM to Stream and stream to MM) with the streaming port exported. I then connect the exported streaming signals to the exported conduit signals of the LVDS SERDES using Verilog. I am getting a timing issue with the msgdma sink valid signal reporting a "long combinational path". Also platform reports a warning that the reset signal must be export with the stream but doing so results in a error.Nios II Application and BSP template creation error
I am looking to create a new "Nios II Application and BSP from Template" but I am getting this error message: I followed the steps in "AN 717: Gen II Hardware Development Tutorial". I am using Quartus 19.4 and followed the steps to install eclipse manually with confirmation of the plugin_customization.ini file. Please help. Thanks,LVDS SERDES using external PLL from IOPLL
Hello, I am using the LVDS SERDES IP with external PLL provided by the IOPLL. I configured the IOPLL as recommended in the LVDS SERDES IP for Cyclone 10 GX but I am getting an error: "ext_<clock name> has a export signal, but <clock name> does not." This is true for all three clock input from the IOPLL to the LVDS SERDES. Any idea on how to fix this?
