KRoma6
New Contributor
4 years agoCyclone 10 GX 40GBASE support
Hello,
I am designing a 40GBASE application with the Cyclone 10 GX. The XCVR transceiver user guide gives limited direction to setting up the platform designer with this protocol.
First, is there a 40GBASE MAC IP for this card? I am assuming you cannot configure four 10GBASE MAC IP to implement 40GBASE.
Second, how is the Enhanced PCS interface width determined?
Third, are there any other specific setting in the Native PHY, reset controller, or PLL to implement 40GBASE?
Fourth, does the reset controller need to be with the same clock as the PHY and PLL?
Finally, is there an example design I can take a look at?
Thanks,
-K