CaptainPrice15
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Re: Pin allocation for PCIe HIP gen 2 x1 with Avalon-MM Interface
Hello @Wincent_Altera Thanks a lot for your reply. No, I do not need the pin for configuration purpose. I have read the document you provided in your reply and do understand that I have the option to select 1.2V, 1.5V, or 1.8V compatible I/O standard. That being said, as seen in the screenshot I attached in one of my previous replies, the Quartus software doesn't allow me to allocate the nPERST pin to any other IO. It is reluctant that I assign the pin AB11 to it; which is unfortunately not possible for me.Re: Pin allocation for PCIe HIP gen 2 x1 with Avalon-MM Interface
Hello @Wincent_Altera , Thanks a lot for your reply. I am using the 10CX150YF780E5G. I tried placing the perst pin on other banks where 1.8V is provided, but I don't know why, the fitter would like to place the perst only on AB11 (please see screenshot.) The assigned pin for perst (Pin E22) as seen in the screenshot is in bank 2L which I have supplied with 1.8V.Pin allocation for PCIe HIP gen 2 x1 with Avalon-MM Interface
I wish to use the Intel HIP for cyclone 10GX with a F780 package. I wish to use only 1 lane of PCIe 2.0 with Avalon-MM as interface. The quartus software is allowing me to place the tx pin pair only on the pins W28 and W27, the rx pin pair only on pins v26 and v25. The worse part being that it is allowing me to place the 'perst' pin only on the pin AB11 which is impossible for me. I am already uisng this pin, and the bank 2A (which contains the pin AB11) with an IO Voltage of 1.35V while the 'perst' pin needs 1.8V. Is there any wayout from this? I do not wish to redesign my custom board and change all the connections from bank 2A only for the 'perst' pin to get the pin AB11. Any quick help is appreciated. Thanks in advance!
