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CaptainPrice15's avatar
CaptainPrice15
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6 months ago

Pin allocation for PCIe HIP gen 2 x1 with Avalon-MM Interface

I wish to use the Intel HIP for cyclone 10GX with a F780 package. I wish to use only 1 lane of PCIe 2.0 with Avalon-MM as interface. The quartus software is allowing me to place the tx pin pair only ...
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CaptainPrice15's avatar
CaptainPrice15
Icon for New Contributor rankNew Contributor
5 months ago

Hello @Wincent_Altera

Thanks a lot for your reply. No, I do not need the pin for configuration purpose. I have read the document you provided in your reply and do understand that I have the option to select 1.2V, 1.5V, or 1.8V compatible I/O standard. That being said, as seen in the screenshot I attached in one of my previous replies, the Quartus software doesn't allow me to allocate the nPERST pin to any other IO. It is reluctant that I assign the pin AB11 to it; which is unfortunately not possible for me.

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    5 months ago

    Ho @CaptainPrice15 ,

    No, I do not need the pin for configuration purpose.
    >> Sorry I missunderstanding your question, thanks for clarified.

    Quartus software doesn't allow me to allocate the nPERST pin to any other IO. It is reluctant that I assign the pin AB11 to it; which is unfortunately not possible for me.
    >> If I go through the device schematic diagram https://cdrdv2-public.intel.com/649849/c10gx-dev-kits-board-a1-release.pdf
    >> AB11 was only PCIe_perst that we have for this device
    >>


    >> As it is only perst for PCIe, we are suggest to use AB11.

    Regards,

    Wincent