KCMurphy
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LPDDR3 Calibration sometimes not completing Arria 10
We have a board design with an Arria 10 and a single Micron LPDDR3 IC. Mostly it works. But on occasion, the device comes out of reset with the EMIF PLLs locked, but neither cal_success nor cal_fail indicated. The EMIF is not functional at this time. This may happen after a board reset from a working condition. Under software control, the EMIF global_reset_n line can be puled low, but this does not fix the issue. A board reset of the Arria also does NOT fix the problem once this mood is entered, only a power-cycle of the board does.902Views0likes3CommentsRe: Constraints for ADC data input
In the simplest form, we were having trouble with data from an ADC. All data/clock lines from ADC short and same length. Data transitions on falling edge of ADC-provided clock. If the clock is 100MHz, what is the best input_delay to use? We assumed that defining the actual clock and saying the data delay was about 1/2 the period (to account for the negative edge, would allow correct setup time calculation. But it wasn't working. Later we found a different reason it was not working. But as long as I'm here, what is the proper set_input_delay method for this fairly simple setup?2.3KViews0likes0CommentsRe: Questa Simulation Not Showing All Needed Variables
It's probably a good thing to read msim_setup.tcl and create your own startup call into that, using ld_debug and enum_debug as shown in the verbose output from the setup tcl. But I wouldn't go so far as to modify them directly as they can get recreated by Quartus. Here's my normal startup: do ../mentor/msim_setup.tcl set TOP_LEVEL_NAME testbench_test set FORCE_MODELSIM_AE_SELECTION true set SILENCE true elab_debug -suppress 3016 -t 1ps do wave.do and my rebuild when I create a new IP module in quartus and generate a new script for msim. do ../mentor/msim_setup.tcl set TOP_LEVEL_NAME testbench_test set FORCE_MODELSIM_AE_SELECTION true set SILENCE true ld_debug -suppress 3016 -t 1ps8.9KViews0likes0CommentsConstraints for ADC data input
I have an Arria 10 connected to a Linear LTC2165 ADC capable of SDR or DDR operation. The ADC expects a differential clock provided to time the conversion and produces a differential clock slightly later whose NEGATIVE edge coincides with the data transition in single-ended mode, and with the first of two interleaved half-words in differential DDR mode. See attached diagrams from the LTC datasheet. Note the flipped polarity of CLKOUT. For a sample rate of about 104MHz, It would seem that I want constraints like: create_clock -name {RX_CLKp} -period 9.563 -waveform { 0.000 4.781 } {RX_CLKp} set_input_delay -clock RX_CLKp -max 4.9 [get_ports {RX_D[*]}] set_input_delay -clock RX_CLKp -min 4.7 [get_ports {RX_D[*]}] so that the data timing is aligned to the positive clock edge for Quartus to do its thing. This doesn't seem to work. A second question (for DDR mode) is "how do you define timing when you want to sample the data on BOTH edges of the input clock?" Left to itself, the software will assume that no sampling happens on the negative edge and may not provide a valid sampling period there. Note: RX_CLKp/n uses a dedicated clock input and feeds through an alt_inbuf_diff and then a global clock control block.2.4KViews0likes4CommentsRe: Questa Simulation Not Showing All Needed Variables
The issue here is "optimization" which needs to be turned off for logic debug, and probably always in an FPGA design. For verilog, right click on a source, choose "compile properties" and check "use vopt flow" and maybe you want to select an optimization level under coverage. I believe that these settings are project wide. If you need to look into an Altera IP block, you may have to put a comile option into the msim_setup.tcl file. Haven't tied that. Note: I solved this about a year ago and may be a bit fuzzy on the path.9KViews0likes0CommentsHow to constrain a ADC input to a narrow delay window Arria 10
I have an external ADC which I need to sample with an internally generated clock. Reasons. The ADC data conversion is driven by a clock I output, and I would like to sample it with a derived clock at some phase angle. To do this reliably, I need to be able to constrain both the output clock and the input data paths to some known delay window. At first blush it looks like set_max_delay and set_min_delay would do the trick, but those directives seem to be aimed at setup and hold time respectively, which is not what I want. I simply want to control the routing so that the delay is known (and repeatable). I can set skew, which is nice, but I still need to constrain the delay time.1.1KViews0likes2Comments