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VHDL_User's avatar
VHDL_User
Icon for New Contributor rankNew Contributor
4 years ago

Questa Simulation Not Showing All Needed Variables

I am using Quartus to write my program in and am trying to simulate this in Questa. My program compiles in both applications. When I begin simulation in Questa, some inputs and outputs are missing. T...
KCMurphy's avatar
KCMurphy
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Look in the manuals for the vhdl compile command line. In verilog you want the -vopt flag.