Occasional ContributorConstraints for ADC data input
I have an Arria 10 connected to a Linear LTC2165 ADC capable of SDR or DDR operation.
The ADC expects a differential clock provided to time the conversion and produces a differential clock slightly later whose NEGATIVE edge coincides with the data transition in single-ended mode, and with the first of two interleaved half-words in differential DDR mode.
See attached diagrams from the LTC datasheet. Note the flipped polarity of CLKOUT.
For a sample rate of about 104MHz, It would seem that I want constraints like:
create_clock -name {RX_CLKp} -period 9.563 -waveform { 0.000 4.781 } {RX_CLKp}
set_input_delay -clock RX_CLKp -max 4.9 [get_ports {RX_D[*]}]
set_input_delay -clock RX_CLKp -min 4.7 [get_ports {RX_D[*]}]
so that the data timing is aligned to the positive clock edge for Quartus to do its thing.
This doesn't seem to work.
A second question (for DDR mode) is "how do you define timing when you want to sample the data on BOTH edges of the input clock?" Left to itself, the software will assume that no sampling happens on the negative edge and may not provide a valid sampling period there.
Note: RX_CLKp/n uses a dedicated clock input and feeds through an alt_inbuf_diff and then a global clock control block.
