Occasional Contributor
New ContributorI think you may want this:
create_clock -name {RX_CLKp} -period 9.563 -waveform { 0.000 4.781 } {RX_CLKp}
create_clock -name {RX_ADC_CLK} -period 9.563 -waveform {4.781 9.563}
set_input_delay -clock RX_ADC_CLK -max 0.0 [get_ports {RX_D[*]}]
set_input_delay -clock RX__ADC_CLK -min 0.0 [get_ports {RX_D[*]}]
That creates a "virtual clock" that is sending the ADC data, and saying it is shifted by half a cycle. (I did not look at the LT data sheet, but think you described it that way). With this you should see a setup relationship of 4.781ns and hold relationship of -4.781ns. What that means is if the clock and data delays in the FPGA were perfectly aligned, you would meet setup/hold slack by 4.781ns. Another way to say it is they could skew from each other by +/-4.781ns and still meet timing. (Though the fitter should try to align them, though having a PLL in ssync mode will help)
Next thing you need to do is account for the clock/data skew coming out of the ADC. Let's say it's +/-2ns, and let's say the board skews are 200ps. Then you would change the input -max value to +2.2ns and the -min value to -2.2ns.
For DDR, there is a long document I wrote a long time ago, if you want to do some reading. Note that there are some templates you can just copy and paste from too:
