Constraints for ADC data input

In the simplest form, we were having trouble with data from an ADC.

All data/clock lines from ADC short and same length. Data transitions on falling edge of ADC-provided clock. If the clock is 100MHz, what is the best input_delay to use? We assumed that defining the actual clock and saying the data delay was about 1/2 the period (to account for the negative edge, would allow correct setup time calculation. But it wasn't working.

Later we found a different reason it was not working. But as long as I'm here, what is the proper set_input_delay method for this fairly simple setup?