How to constrain a ADC input to a narrow delay window Arria 10

I have an external ADC which I need to sample with an internally generated clock. Reasons. The ADC data conversion is driven by a clock I output, and I would like to sample it with a derived clock at some phase angle.

To do this reliably, I need to be able to constrain both the output clock and the input data paths to some known delay window. At first blush it looks like set_max_delay and set_min_delay would do the trick, but those directives seem to be aimed at setup and hold time respectively, which is not what I want. I simply want to control the routing so that the delay is known (and repeatable).

I can set skew, which is nice, but I still need to constrain the delay time.