BigHandsomeBee
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Re: Simualte HLS IP with Qsys
Thanks for the reply. I'm not asking how to simulate HLS IP. What I'm trying to do is that, I have a verified HLS IP, and I need to integrate this IP into a Qsys project, connecting it with other component/IPs, to build a project. After building the Qsys project, I need to run the simulation to verify the project. Then I need to use ModelSim to simulate the project. But when simulating with ModelSim, it complains that the HLS IP module cannot be resolved, which means, I guess, I need to compile the instantiated HLS IP into a library before simulating the Qsys project with ModelSim. But I don't know how to do that.Mentor Verification AXI IP Simulation Error with ModelSim-AE
I'm using Quartus Prime Pro 21.2, and I'm running the example following the document provided by Intel. Chapter 12 https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/mentor_vip_axi34_ae_usr.pdf I'm following the process: 1. Open Qsys project 2. Generate HDL 3. Run the command line: vsim -mvchome=$QUARTUS_ROOTDIR/../ip/altera/mentor_vip_ae/common -c -do example.do I got the following error: It seems like that there is some issue with the provided testbench file top.sv. How could I resolve this error? Thank you.What's the reason rejecting register duplication?
I'm trying to manually duplicate a register with the following assignment: set_instance_assignment -name DUPLICATE_REGISTER -to *is_all_mt_veri_not_empty* As shown in the figure, the duplication is rejected with the reason "synchronization register". I was wondering what's the meaning of this reason? I did not find any document elaborating the reason more detailedly. Thank you.quartus_fit was unexpectedly terminated by signal 9
I'm using Quartus Prime Pro 21.2. When I synthesized a design on Stratix 10, I got an error: Error(20549): Current module quartus_fit was unexpectedly terminated by signal 9. This may be because some system resource has been exhausted, or quartus_fit performed an illegal operation. You can view system resource requirements on the System and Software Requirements page of the Intel FPGA website (https://fpgasoftware.intel.com/requirements/). I'm running the software on Ubuntu 20.04 with 32GB RAM.Re: Nios II code only working in debug mode.
Hi @BoonBengT_Altera , Thanks for the reply! I'm using Quartus Prime Pro 21.2 with Stratix 10 device. I re-packed the project file deleting irrelevant files. Please find it in the attachment. I'm pretty sure the .sof file is successfully programmed to the hardware. Another thing that I have found recently is that if I downloaded the .elf code multiple times, e.g. type command "nios2-download -g xxxx.elf" in terminal multiple times, occasionally the downloaded code can work while most of the time it does not work. No timing error was reported in the compilation report, so I'm not sure how this nondeterministic behavior happens. Thank you. Yu
