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Re: Initializing inferred RAM from a text file
Hi Sheng, Thanks for your answer. For the In-System Memory Content Editor, I was curious about enabling the feature for the RAMs inferred in HDL, not by a megafunction wizard. I assume it is not possible from your answer but I am not sure. Also, as you have mentioned this feature is for single-port RAMs, does it mean that there is no way I can enable this feature for dual-port RAMs? Thanks, Efe2.1KViews0likes0CommentsDCFIFO Mixed Width Recovery Removal Timing
Hi, It is described here that for older versions of Quartus, DCFIFO with mixed width which read width is smaller than the write width contains an connection error in design which causes Recovery faults. However, there is not any solution mentioned. I am also facing this issue in a design which I have a DCFIFO fits the properties above and has a aclr signal externally synchronized to the write clock. What should be done if someone is obligated to use older versions of Quartus and facing this problem? Thanks, EfeSolved1KViews0likes3CommentsInitializing inferred RAM from a text file
Hello, I have written a simple dual-port RAM in VHDL following the single-port RAM example from Quartus, and I want to initialize this RAM using an external text file containing binary values. However, when I compile the design and check the contents of the RAM, everything is 0. What can be the problem? I am posting my dual-port RAM code and initialization text file. Also, how can I use the In-System Memory Content Editor if I infer memory using HDL? Is there even a way to do that? -- Quartus Prime VHDL Template -- Single-port RAM with single read/write address and initial contents library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use std.textio.all; entity dual_port_ram is generic ( FILE_PATH : string := "ram_content_bin.txt"; DATA_WIDTH : natural := 8; ADDR_WIDTH : natural := 6 ); port ( clk : in std_logic; addr_a : in std_logic_vector((ADDR_WIDTH - 1) downto 0); addr_b : in std_logic_vector((ADDR_WIDTH - 1) downto 0); data_a : in std_logic_vector((DATA_WIDTH-1) downto 0); data_b : in std_logic_vector((DATA_WIDTH-1) downto 0); wren_a : in std_logic; wren_b : in std_logic; q_a : out std_logic_vector((DATA_WIDTH -1) downto 0); q_b : out std_logic_vector((DATA_WIDTH -1) downto 0) ); end dual_port_ram; architecture rtl of dual_port_ram is -- Build a 2-D array type for the RAM subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0); type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t; impure function init_ram_bin return memory_t is file text_file : text open read_mode is FILE_PATH; variable text_line : line; variable ram_content : memory_t; variable bv : bit_vector(ram_content(0)'range); begin for i in 0 to 2**ADDR_WIDTH - 1 loop readline(text_file, text_line); read(text_line, bv); ram_content(i) := To_StdLogicVector(bv); end loop; return ram_content; end function; -- Declare the RAM signal and specify a default value. Quartus Prime -- will create a memory initialization file (.mif) based on the -- default value. signal ram : memory_t := init_ram_bin; begin process(clk) begin if(rising_edge(clk)) then if(wren_a = '1') then ram(to_integer(unsigned(addr_a))) <= data_a; end if; end if; end process; q_a <= ram(to_integer(unsigned(addr_a))); process(clk) begin if(rising_edge(clk)) then if(wren_b = '1') then ram(to_integer(unsigned(addr_b))) <= data_b; end if; end if; end process; q_b <= ram(to_integer(unsigned(addr_b))); end rtl; 000000000 100000010 011110000 000000000 101001100 001001011 101000000 011000011 100000001 100000010 000000000 010010000 000000000 000000000 000000000 010010011 Thanks, Efe2.1KViews0likes4CommentsNios II memory location of a variable
Hi, I am using Quartus 14.1 and I am trying to write a test application for DDR3 connected to Nios II. I have successfully created the hardware and synthesized. And I want to do some write/read tests on DDR3 using Nios. First, I create an array named write_data and write it to DDR location 0. Then, I read the DDR starting from location 0 into an array named read_data. However, when I check the pointers of elements of write_data and read_data, I see their addresses are in the same address space as DDR. Does it mean that these variables already on the DDR? I want them to be in onchip memory actually. Is there any way to declare variables in memory space I want? Thanks. Efe661Views0likes0CommentsWhere does channel data stored when the AXI interconnect is busy?
Assume the AXI interconnect is busy at the moment, and there is a master that wants to read/write something to a slave. So, is this request stored temporarily at the master itself or at the master/slave interface or at the AXI interconnect? I assume these signals coming from channels should be stored in some FIFOs. However, I do not know where are these FIFOs. If it is a design-specific problem, how Intel implements it?990Views0likes2CommentsMIF file
Hello, I want to initialize my RAM using .mif file. I want to store 2 different width of data in the memory, one is 16-bit and the other is 18-bit. Therefore, I have decided to use 18-bit wide RAM. However, when I try to fill the .mif file I got confused. I want to write the initialization data in HEX format, addressing in DEC format. For example, if I want to have 0x0ABC as 16-bit data in the address 10d, what should I write? 10 : 00ABC; Is this right? Also if I want to have 11_1010_1011_1100_1101b (18-bit) in the address 15d, what should I write? 15 : FABCD; Is this also right? If not, can you guide me a little? Thanks.Solved5.5KViews0likes3Comments- 2.7KViews0likes0Comments
Quartus qt5.15
Hello, I am using Ubuntu Desktop 20.04 LTS and Quartus Prime Lite 20.1. When I enter quartus into terminal, this error occurs: efe@efeASUS:~$ quartus quartus: /usr/lib/x86_64-linux-gnu/libQt5Core.so.5: version `Qt_5.15' not found (required by quartus) How can I solve it? Thanks.Solved2.7KViews0likes2Comments