Where does channel data stored when the AXI interconnect is busy?

Assume the AXI interconnect is busy at the moment, and there is a master that wants to read/write something to a slave. So, is this request stored temporarily at the master itself or at the master/slave interface or at the AXI interconnect? I assume these signals coming from channels should be stored in some FIFOs. However, I do not know where are these FIFOs.

If it is a design-specific problem, how Intel implements it?