Differential Signal Transmitter on Agilex 5 FPGA Modular Dev Kit
We will use the SOM Module of the Agilex 5 FPGA E-Series 065B Modular Development Kit (MK-A5E065BB32AES1) for a new project with our own designed carrier board. For this design we need multiple differential transmit and receive signals from I/O Bank 2A_B and 2A_T (→ 1.2V bank supply). We started with a basic design to evaluate usable I/O Standards. We have seen that we can use differential receiver with the 1.2V bank supply but it is not possible to use "True Differential Signaling" on transmit pins with 1.2V bank supply. For our purpose it is necessary to generate differential transmit signals correctly working with LVDS inputs on the receiver site. Is there an alternative differential signal output generating a correct LVDS signal for a LVDS receiver working with the 1.2V bank supply (e.g. POD12 with special termination)? What happens when setting differential transmit and receive pins to "1.3V True Differential Signaling" to get Quartus running without an error but physically using only 1.2V bank supply? Will this only decrease signal swing on transmit pins or is this not working? Or could this damage the FPGA transmit and receive pins of the FPGA? The SOM schematic does not show any possibility to disconnect the I/O Banks 2A_B and 2A_T from onboard 1.2V supply to use an alternative external 1.3V supply. Is there the a possibility to supply these banks externally by 1.3V? Which other alternatives do we have to get differential signaling output working?
MAX10 10M50 Development KIT Triple Speed Ethernet problem
Greetings to all of the ALTERA Experts, I have been trying to get a Gigabit Ethernet interface working on an ALTERA MAX10 10M50-C Development kit and keep hitting a bit of a brick wall when tying to communicate with the MARVEL ALASKA 88E1111 PHY. It does not appear to respond correctly when i try to read for example the PHY ID register (address x02) which should respond with the value 0x041 but instead sends back 0x7fff. I am using a System Verilog HDL approach to both instantiate the ALTERA Triple speed IP core in MAC only mode, with 2K word FIFOs, and full duplex 10/100/1000. The IP is set to work in Gigabit mode. When i connect the board to a windows 10 PC using an Ethernet cable i can see the Yellow LED lit up on the Dev KITS PHY connector and when i test the connection on the windows 10 PC it says it is up and connected. But when i try to send any Ethernet packets (i am using IPV4 + UDP as packet payload) nothing gets through to the PC. I have verified this as well using WIRESHARK which shows me no ethernet frames are coming in from the MAX10 Dev kits end. I have set the Triple speed Ethernet IP cores mac0/mac1 register to this random value: 48'h321C23174ACB I think this is OK and what the Triple Speed Ethernet User Guide says. Please correct me if my thinking is wrong though ? Questions: a) Does any body know of any errata / bugs with this Development KIT OR with the MARVELL PHY ? b) Can anybody point me to a Git Hub which has a known working example using this ALTERA Dev Kit along with this MARVELL PHY ? This can use either a HDL approach (like i am trying to use here) or a NIOSV softcore processor approach. c) The MAX10 Dev Kit has 2 Ethernet PHYS. A and B. I think that the MAX10 10M50-C Dev Kit sets its A MARVELL PHY Address to 0x0 and its B side MARVELL PHY Address to 0x1 BUT its not easy i found to figure out the PHY addresses. If somebody can please show me how to properly derive the PHY ADDRESSES for both the MARVELL 88E1111 devices for PHY A (ETHERNET A) and PHY B (ETHERNET B) on the MAX10 10M50-C Dev Kit Board Schematic) i will be very grateful ! Thanks for any help, Dr Barry H
Technical Assistance Request for Stratix® 10 SX SoC Development Kit (so#488775)
Hello all, PN#DK-SOC-1SSX-H-D PO#029-CA574 QTY: 1 Our customer used above board and had below questions, could you help check and give us solutions? “Please help to confirm whether the FMC IO voltage on this development board supports 1.2 V. If it is supported, could you please advise how the FMC IO voltage can be configured to 1.2 V (for example, via hardware settings, jumpers, or power configuration)? Any relevant documentation or guidance would be greatly appreciated.” Thank you.
Ubuntu 18 LXDE image for DE10 Nano board
Hello, I wanted to install CUPS in Linux running on HPS side of DE10 Nano, but the current version of Ubunto is 16.04 in LXDE image that comes with it. THat version has reached to EOL, so I was wondering if I could find LXDE image with Ubuntu 18 and could easily install CUPS on it via APT update. Thanks in advanceEPM9320LI84-20
Hello! Could you please clarify something? Within the same batch of EPM9320LI84-20 FPGAs, the marking quality varies significantly, which is especially noticeable in the letter A in the ALTERA logo. This is not an isolated case within the batch—there are several chips with the same issue. Could this happen during manufacturing? As you understand, these chips were discontinued long ago and are no longer available from official distributors, so we have to source them from less reliable suppliers. Please respond as soon as possible. Thank you!JTAG Chain Broken – Unable to Program Agilex 5 Modular Development Board
Hi, I recently started working with the Agilex 5 Modular Development Board, and it suddenly can no longer be programmed. The USB cable in use is known to be working. When I connect the cable, it is detected, but when I run the “Auto Detect” option in the Quartus Programmer, I receive the following message: When running the JTAG Chain Test, I see the following result: I also tried using the Configuration Debugger, but when I attempt to select the hardware cable, I encounter Error code 87: I would appreciate any help in resolving this issue, and I can provide additional details or logs if needed.
EMIF HPS errors after upgrading to Quartus 25.3
So I'm trying to upgrade an Agilex-5 project from Quartus 25.1 to 25.3 but the project no longer compiles with errors relative to the EMIF HPS IP. I'm using an Agilex 5 FPGA E-Series 065B Premium Devkit. The project was based in the GSRD for Quartus 25.1 (QPDS25.1_REL_GSRD_PR) and had a few modifications, working in version 25.1. Firstly, when upgrading to Quartus 25.3, the auto-update does not work with errors to the Agilex-5 HPS IP and EMIF HPS IP. I'm forced to upgrade manually which also results in errors but fixed with this workaround: https://www.intel.com/content/www/us/en/support/programmable/articles/000102053.html In the end I can Generate HDL sources from Platform Designer but compilation stops with errors in the Fitter stage: I've noticed that the new EMIF HPS IP version has a difference in the signal mem_0_bg that only has 1 bit in the latest version but was 2-bit wide in the previous versions. I don't know if the problem comes from this: Another interesting thing that I found is that in the latest GSRD project (QPDS25.3_REL_GSRD_PR) the EMIF HPS IP used is not the latest version (4.1.0) but a previous one (4.0.0). So I'm guessing someone from Altera already discovered some sort of problem here: Looking for advice on how to proceed.
