EPM9320LI84-20
Hello! Could you please clarify something? Within the same batch of EPM9320LI84-20 FPGAs, the marking quality varies significantly, which is especially noticeable in the letter A in the ALTERA logo. This is not an isolated case within the batch—there are several chips with the same issue. Could this happen during manufacturing? As you understand, these chips were discontinued long ago and are no longer available from official distributors, so we have to source them from less reliable suppliers. Please respond as soon as possible. Thank you!
JTAG Chain Broken – Unable to Program Agilex 5 Modular Development Board
Hi, I recently started working with the Agilex 5 Modular Development Board, and it suddenly can no longer be programmed. The USB cable in use is known to be working. When I connect the cable, it is detected, but when I run the “Auto Detect” option in the Quartus Programmer, I receive the following message: When running the JTAG Chain Test, I see the following result: I also tried using the Configuration Debugger, but when I attempt to select the hardware cable, I encounter Error code 87: I would appreciate any help in resolving this issue, and I can provide additional details or logs if needed.
EMIF HPS errors after upgrading to Quartus 25.3
So I'm trying to upgrade an Agilex-5 project from Quartus 25.1 to 25.3 but the project no longer compiles with errors relative to the EMIF HPS IP. I'm using an Agilex 5 FPGA E-Series 065B Premium Devkit. The project was based in the GSRD for Quartus 25.1 (QPDS25.1_REL_GSRD_PR) and had a few modifications, working in version 25.1. Firstly, when upgrading to Quartus 25.3, the auto-update does not work with errors to the Agilex-5 HPS IP and EMIF HPS IP. I'm forced to upgrade manually which also results in errors but fixed with this workaround: https://www.intel.com/content/www/us/en/support/programmable/articles/000102053.html In the end I can Generate HDL sources from Platform Designer but compilation stops with errors in the Fitter stage: I've noticed that the new EMIF HPS IP version has a difference in the signal mem_0_bg that only has 1 bit in the latest version but was 2-bit wide in the previous versions. I don't know if the problem comes from this: Another interesting thing that I found is that in the latest GSRD project (QPDS25.3_REL_GSRD_PR) the EMIF HPS IP used is not the latest version (4.1.0) but a previous one (4.0.0). So I'm guessing someone from Altera already discovered some sort of problem here: Looking for advice on how to proceed.
DE10-nano HPS boot from EPCS
Hello, I am currently trying to setup LoanIO on a DE10-nano so i can access the PHYs RGMII0 signals from the FPGA. According to the Cyclone V Manual, the HPS registers have to be set up in the preloader for this. So i follow this guide to build the u-boot-spl: https://www.rocketboards.org/foswiki/Documentation/UpdatePreloaderUBootOnDE10NanoOnWindows10OS Then converted it to a .hex file to initialize the on-chip Memory following to this guide: https://www.rocketboards.org/foswiki/Documentation/BootFromFPGA150 Then recompile the design and finally generate the .jic file to configure everything from EPCS64. Now the FPGA part of my design is running but the preloader does not seem to be executed. I am using Quartus Prime 24.1std and u-boot branch socfpga_v2025_07. I also tried setting SPL_TEXT_BASE to 0xC0000000 and CONFIG_SPI_BOOT inside the menuconfig. Am i missing any relevant flags or is the problem elsewhere? Best regards."No Video Input" message on the monitor running Display port design example for Arria 10 SX SoC
Hi, I am stuck trying to test Display Port on my Arria 10 SX SoC board. I need TX only design example. I tried to download full design example from Intel/Altera web sites, but mostly they are for older Quartus versions or for FMC daughter cards. I want to test Display Port onboard connector. My Quartus version is Quartus Pro 25.1, device - 10AS066N3F40E2SG1 Also I tried to generate design example in Platform Designer and I succeeded to receive EDID from monitor and it seems that handshake is done, but I see only "No Video Input" message on my monitor. I spend more than a week discovering the issue and I assume that PMA settings might be wrong or incorrect link rate/clock frequencies. Thanks in advance for any help!SFP+ ref clock (program clock cleaner?)
Hi, I'm working with Arria 10 SoC dev kit and trying to use SFP+ ref clock. I don't have any information on ref clock frequency on LMK_SFPCLK(P/N) that comes from clock cleaner (U26). I need to have ref clock by like 322.265625 Mhz, so do I need to program U26 (clock cleaner)?? Where I can find the software to do so? Another question is what is the default frequency running on LMK_SFPCLK ? Thanks
