"No Video Input" message on the monitor running Display port design example for Arria 10 SX SoC
Hi, I am stuck trying to test Display Port on my Arria 10 SX SoC board. I need TX only design example. I tried to download full design example from Intel/Altera web sites, but mostly they are for older Quartus versions or for FMC daughter cards. I want to test Display Port onboard connector. My Quartus version is Quartus Pro 25.1, device - 10AS066N3F40E2SG1 Also I tried to generate design example in Platform Designer and I succeeded to receive EDID from monitor and it seems that handshake is done, but I see only "No Video Input" message on my monitor. I spend more than a week discovering the issue and I assume that PMA settings might be wrong or incorrect link rate/clock frequencies. Thanks in advance for any help!
Device stopped receiving config data: Internal error (0x0000, 0x00000000, 0x1800).
Using Agilex AGFB014R24A (E-Tile board). .jic flashes successfully, but no UART logs are observed after boot. Observed attached logs attached When programming the corresponding .sof via JTAG, configuration fails at ~86%. Device has stopped receiving configuration data Error message received from device: Internal error. (Subcode 0x0000, Info 0x00000000, Location 0x00001800) Operation failed Ended Programmer operation Looking for clarification on this internal error and recommended workaround.
EMIF HPS errors after upgrading to Quartus 25.3
So I'm trying to upgrade an Agilex-5 project from Quartus 25.1 to 25.3 but the project no longer compiles with errors relative to the EMIF HPS IP. I'm using an Agilex 5 FPGA E-Series 065B Premium Devkit. The project was based in the GSRD for Quartus 25.1 (QPDS25.1_REL_GSRD_PR) and had a few modifications, working in version 25.1. Firstly, when upgrading to Quartus 25.3, the auto-update does not work with errors to the Agilex-5 HPS IP and EMIF HPS IP. I'm forced to upgrade manually which also results in errors but fixed with this workaround: https://www.intel.com/content/www/us/en/support/programmable/articles/000102053.html In the end I can Generate HDL sources from Platform Designer but compilation stops with errors in the Fitter stage: I've noticed that the new EMIF HPS IP version has a difference in the signal mem_0_bg that only has 1 bit in the latest version but was 2-bit wide in the previous versions. I don't know if the problem comes from this: Another interesting thing that I found is that in the latest GSRD project (QPDS25.3_REL_GSRD_PR) the EMIF HPS IP used is not the latest version (4.1.0) but a previous one (4.0.0). So I'm guessing someone from Altera already discovered some sort of problem here: Looking for advice on how to proceed.Fitter error in A5ED043AB23AI2V Example design
Hi, I have tried using the example design of the A5ED065BB32AE4SR0 development kit and modified the part number to A5ED043AB23AI2V. During compilation, I am encountering a fitter error when both PCIe and USB 3.1 are enabled together. However, I am able to compile successfully when using each interface individually. Could you please help me understand how to resolve this issue?Agilex5 Eagle ES, NIOS-V + TSE IP
Trying to setup a NIOS-V with a TSE MAC to utilize the ethernet interface connected to the FPGA on the Agilex Eagle ES devkit. NIOS executes firmware and able to read the PHY registers. But when connecting the ethernet cable nothing seems to happen, status registers does not change and no link-up is reported. Does anyone know of any examples using the NIOS-V and TSE with RGMII interface that I can look at to troubleshoot the issue ?
