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pmarques's avatar
pmarques
Icon for New Contributor rankNew Contributor
29 days ago
Solved

F2SDRAM max burst length - Agilex5

Hello,

I'm using an Agilex 5 E-Series 065B Premium Devkit.

I have successfully accessed the DDR4 through the F2SDRAM interface using a 256-bit data bus width and INCR burst type.

The problem is I can't set AxLEN > 128 or the AXI4 interface will break. I would like to use AxLEN = 256 for maximum throughput.

According to the Hard Processor System Technical Reference Manual: Agilex 5 SoCs (v25.3), page 799, Table 333:

  • AxLEN[7:0] - INCR burst type is 1 to 256 transfers.

So AxLEN = 256 should be supported. Can anyone clarify if the maximum burst length is indeed 128 or 256 ?

Best regards.

soc devkit
  • KianHinT_altera's avatar
    KianHinT_altera
    12 days ago

    Hi, 

    Apologies for the delayed response as previously our embedded team did not monitor this forum category for embedded related question until we are notified by other teams .

    As for this issue, I saw there is a requirement that any transaction cannot cross a 4KB boundary in the AXI protocol document (https://developer.arm.com/documentation/ihi0022/latest/) . Is your transaction adheres to this requirement?

    Perhaps you can refer to this demo example 

    https://github.com/altera-fpga/agilex5-demo-hps2fpga-interfaces/blob/main/documentation/09_menu_p_hw_f2sdram_bridge.md

     

    Thanks

    Regards

    Kian

3 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    25 days ago

    When you say the interface breaks, do you mean you simply can't compile the design (the parameter editor won't let you select 256) or that you've compiled the design with it set to 256 and it's not working?

    Usually if it's a parameter editor issue, some other parameter you've set is preventing you from selecting the value you want.

    • pmarques's avatar
      pmarques
      Icon for New Contributor rankNew Contributor
      25 days ago

      Hi sstrell​,

      The design is compiled successfully. The ARLEN/AWLEN are signals of the AXI-4 interface, not parameters from the editor.

      When I say the interface breaks, this is what I mean:

      WRITE OPERATION:

      • The F2SDRAM interface accepts the first transaction with a burst length of 256 but during the second transaction, WREADY drops and it's never asserted again until a board reset.
      • There's also no activity on BRESP/BVALID to indicate success or failure of the write transaction. Both stay low.

      READ OPERATION:

      • Although I'm asking for a burst length of 256 (ARLEN) I'm only receiving 128 samples before RLAST is asserted.
      • No error on RRESP.

      This happens when I set ARLEN/AWLEN with any value > 128. Values of 128 and lower work as expected.

      I can attach logs from the Signal Tap Analyzer if it's easier to illustrate the problem.

  • KianHinT_altera's avatar
    KianHinT_altera
    Icon for Frequent Contributor rankFrequent Contributor
    12 days ago

    Hi, 

    Apologies for the delayed response as previously our embedded team did not monitor this forum category for embedded related question until we are notified by other teams .

    As for this issue, I saw there is a requirement that any transaction cannot cross a 4KB boundary in the AXI protocol document (https://developer.arm.com/documentation/ihi0022/latest/) . Is your transaction adheres to this requirement?

    Perhaps you can refer to this demo example 

    https://github.com/altera-fpga/agilex5-demo-hps2fpga-interfaces/blob/main/documentation/09_menu_p_hw_f2sdram_bridge.md

     

    Thanks

    Regards

    Kian