Agilex 5 GTS Reset Sequencer Intel FPGA IP : what value to set to i_refclk_bus_out with a PCIe IP ?
Hello, Using a PCIe IP in Root Port on a AGILEX 5, I have to use the GTS Reset Sequencer Intel FPGA IP configured in PCIe. With Quartus 2025.1, the i_refclk_bus_out port appears on the GTS Reset Sequencer Intel FPGA IP. There is no port on the PCIe IP to connect to port i_refclk_bus_out. So, to which signal or to what value the port i_refclk_bus_out must be connected ? Thanks. Serge
How to calculate Setup slack and Hold slack?
I'm having trouble understanding how to calculate Setup slack and Hold slack correctly. According to the Intel Quartus Timing Analysis manual, Setup slack is calculated as Data Required Time (Setup) minus Data Arrival Time, and Hold slack is calculated as Data Arrival Time minus Data Required Time (Hold). However, no matter how I calculate it, my results never seem to match up. I've been spending a lot of time trying to figure out the concept of hold and setup, but it's been challenging. Is it normal to find these concepts difficult to grasp? Can someone explain the correct algorithm for calculating Setup slack and Hold slack? I've referred to the following articles as my reference: https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-software/user-guides.html I would greatly appreciate any help or insights. Thank you in advan ce!
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Stratix 10 MCDMA host: Queue reset failed
Hello, I have been trying to get an MCDMA example design working on a Stratix 10 MX device (1SM21BEU2F55E2VG). You can consider me a beginner with the Intel FPGAs. The project details are as follows. Device side ----------------- Project: Platform designer project with H-tile PCIe MCDMA with AVMM interface. PCIe configuration - Gen3x16 512-bit interface, 250 MHz No of PFs - 1 Everything else is set to default, as this is a slightly modified version of the basic example design generated by Quartus. refclk - connected to differential PCIe clock PCIE_REFCLK_P and PCIE_REFCLK_N pin_perst - connected to PCIe PERST# npor - tied to 1 in the top level wrapper Verilog module xcvr - PCIe interface The top-level wrapper only instantiates this, sets npor to 1, and passes every other signals. The hip_ctrl and hip_pipe are left unconnected in the wrapper. The design compiles properly, and the sof file can be programmed without error. ----------------------- Host side ----------------------- On the host side, I followed the steps mentioned in the MCDMA example user guide. https://www.intel.com/content/www/us/en/docs/programmable/683517/23-4/introduction.html The device is listed the lspci output and shows up the BAR regions. However, when I try to run any of the test programs in the software/user/cli, nothing runs successfully (this driver and user utilities/examples are also generated as part of the example MCDMA project). Most of the time the error is "Queue reset failed" or the programs hang without any output. Reading device memory via the supplied devmem utility always returns 0xFFFFFFFF. My guess is something wrong with the reset logic/process, however I am unable to fix it so far and it feels like I am missing something obvious. Any lead in this regard would be helpful. Let me know if you need more information in this context. Thanks and regards, Arnab
JESD204C CRC occur CRC error...Debug issue point?
We are using Agilex F-tile and are testing it using JESD204C IP on the FPGA. There were various issues with the JESD 204C TX, but it was confirmed that it is currently operating normally. However, in the case of JESD RX, the problem is still being debugged. Our current problems are as follows: 1. The CDR is normally displayed as “Locking”. 2. SH Lock is also displayed as “Locking” normally. 3. emb_lock is also displayed as “Locking” normally. However, the CRC Error says "error" occurs once every 32 symbols. JESD204C lock status JESD204C lock status1 JESD204C lock status2 Of course, the 128 bits received are also not output as desired. In the case of the other side (JESD TX), it is M company's RFIC, and the current RX is 2LANE/16G (245 .76Msps) is being used. Currently, we are using the PRBS checker, but we cannot guarantee that the function is normal. (It is doubtful whether the data on the Tranceiver side is normal.) I am curious if there is a way to debug CRC errors if the PRBS function cannot be used. Also, I wonder if only the CRC problem may occur if there is a problem with the PHY characteristics (electrical characteristics) of the signal. (The lock-related bits are normal, but only the payload can be a problem...) First of all, thank you for your reply.
How to implement LFPS in Cyclone 10 GX transceiver IP
Hi, I am gonna design a USB3.0 port by using the Cyclone 10GX transceiver IP. In USB3.0/3.1 it needs to send a side band signal, Low frequency Period Signal(LFPS) to other partners . Is there anyone knowing how to combine it into the transceiver? Very appreciated!XCVR Reset Controller
We are using an Arria 10 device, 10AS057N2F40E2SG, with some JESD204 Receive only channels. The ADC being used is the T.I. ADC09QJ800AAV in JMODE = 2 (for 4 lanes, 8b/10b). I have a XCVR reset controller instantiated in the QSYS design along with the JESD itself plus a few other things - extremely similar to the Intel design example for JESD. On further inspection I found that one of the four rx_is_lockedtodata signals is deactivated, causing the various outputs such as rx_ready to be deactivated, and rx_digitalreset to be activated. The rx_analogreset outputs are remaining low. The particular one of the four rx_is_lockedtodata that is lost seems to be almost random. What could be the cause of this regular event? Thanks David
P-tile Debug toolkit design changes
Hi there, I am using Intel Agilex-F series development which uses P-tile. I am trying to enable P-tile Debug took kit on the Intel reference design. I am referring to Section 7.2 of P-tile Debug tool kit. What I want to clarify is if I want o just view the P-tile status information and not configure anything to the registers, is it as simple as below steps: 1. Enable Debug Tool kit in Pcie IP configuration 2. Connect a clock to the xcvr_reconfig_clk port of the instantiation 3. Add a pin constraint to connect the xcvr_reconfig_clk to a 100 MHz clock source. My question is do I need to drive any other signals on the xcvr_reconfig* interface to observe the DebugTool kit? Thanks BinuError (16058): PLLs that use the x1 clock network and same HSSI channel must be in the same bank
I have a working Arria-V design that incorporates multi-rate SDI I/O (using our own logic, not the Altera IP blocks). The design was originally implemented using Quartus 15.0 however I have recently been attempting to update to newer versions of Quartus and have encountered some issues. When compiled with Quartus 15.0, I have intermittent data integrity issues with the various DCFIFOs used in the design to bridge streaming video signals across different clock domains due to the embedded "set_false_path" timing constraints in the DCFIFO IP. I updated the design to Quartus 17.1 which supports the lpm_hint “DISABLE_EMBEDDED_TIMING_CONSTRAINT=TRUE” and added the timing constraints recommended by the FIFO IP User Guide. This improved things quite a bit, but I am still seeing data corruption on some units. I read that the recommended set_max_skew constraint is apparently broken for asynchronous clock groups in Quartus versions up to 20.1 or so and I am now trying to migrate to Quartus 22.1std or 21.1.1. With both of these, when I attempt to compile the design I get the error: Error (16058): PLLs that use the x1 clock network and drive the same HSSI channel must be placed in the same transceiver bank. PLL "HD_Core_VS4KG2_V1v0_5AGXMA5_pipen1b:top|Tx_PLL_HD_5AGX:Tx_PLL_HD|av_xcvr_plls:tx_pll_hd_5agx_inst|pll[0].pll.cmu_pll.tx_pll" and PLL "HD_Core_VS4KG2_V1v0_5AGXMA5_pipen1b:top|Tx_PLL_SD_5AGX:Tx_PLL_SD|av_xcvr_plls:tx_pll_sd_5agx_inst|pll[0].pll.cmu_pll.tx_pll" use the x1 clock network and drive the same HSSI channel, however the PLLs are not assigned to the same transceiver bank. In the Assignment Editor, change the location assignment of the second specified PLL to location "CHANNELPLL_X132_Y53_N33" so the two PLLs are in the same transceiver bank. I have added location constraints and been unable to get past this error. For a sanity check, I went back to the working 17.1 version, pulled the locations for my two Tx PLLs from the chip planner, created location constraints for the two PLLs, and recompiled to make sure everything still worked (it did). I then took the design with location constraints and attempted to build with Quartus 21.1.1 and Quartus 22.1std and I continued to get error 16058. The only thing I can find about this error is that it apparently was a problem with Quartus 17.1 that was fixed in 18.0: https://www.intel.com/content/www/us/en/support/programmable/articles/000082957.html?wapkw=16058 This doesn't match what I see, as 17.1 is working for me but newer versions are failing. And recommendations for how to get around this error, or how to properly constrain max. skew across async. clock domains with Quartus 17.1?
