AVST FIFO and AVST Demultiplexer IP Simulation Behavior
Hi, I am using Quartus version 25.3. I simulated 2 IP's independently and had questions about their behavior. 1. For the Avalon Streaming (AVST) Demultiplexer IP (figure 1) , is there a reason why the endofpacket (eop) signal remains asserted after the packet leaves the output, when I simulate with packet support (figure 2)? Is this normal? AVST Demultiplexer IP version 19.3.1. 2. For the AVST SC FIFO (Figure 3) , is there a reason the negative edge of output eop is unknown (red) (Figure 4)? Is this normal? AVST SC FIFO version 19.3.2. Thank you for the help! AVST Demultiplexer Parameters: AVST Demultiplexer Waveform: AVST SC FIFO Parameters: AVST SC FIFO Waveform:
ALT PLL GUI MESSDED UP ON INVOCATION
Hi All ALTERA Experts, I have a problem setting up a new PLL due to the GUI looking like the mess you can see in my attached screenshot. I am using Quartus Standard edition Version 25.1 I am on a windows 10 machine and all of the other IP GUIs seem to work fine, its just this PLL IP GUI that seems to get messed up. I am using a MAX10 FPGA. Both my PC and Graphics card are working fine. Can anybody suggest why this occurs ? Thanks, Barry
I350 igb driver failed with error -2
Dear Support, My setup is the following, I have a I350 connected to an arm based board (Jetson) over PCIe. On port0 of the I350 there is an external PHY (DP83TG721) connected over SGMII (rx/tx and MDIO). The external PHY is needed for automotive Ethernet. I got the EEPROM Access tool and the accompanying flash images. The I350 gets discovered as a PCIe device and I'm able to flash it using the EEPROM tool. When trying the I350_2-4port_Copper_NO-MNG_1_63 flash image. The igb driver loads correctly and 4 working network interfaces appear, nice. But the goal is to also get the external PHY working. When trying the I350_2-4port_SGMII_NO-MNG_1_63 flash image for SGMII connection with the PHY the driver fails to load nvidia@nvidia-desktop:~$ sudo dmesg | grep igb [ 0.217490] igb: Intel(R) Gigabit Ethernet Network Driver [ 0.217495] igb: Copyright (c) 2007-2014 Intel Corporation. [ 0.217520] igbvf: Intel(R) Gigabit Virtual Function Network Driver [ 0.217526] igbvf: Copyright (c) 2009 - 2012 Intel Corporation. [ 14.102105] igb 0005:01:00.0: Adding to iommu group 57 [ 14.102411] igb 0005:01:00.0: enabling device (0000 -> 0002) [ 14.755600] igb: probe of 0005:01:00.0 failed with error -2 [ 14.757712] igb 0005:01:00.1: Adding to iommu group 57 [ 14.757927] igb 0005:01:00.1: enabling device (0000 -> 0002) [ 15.074173] igb: probe of 0005:01:00.1 failed with error -2 [ 15.074709] igb 0005:01:00.2: Adding to iommu group 57 [ 15.074889] igb 0005:01:00.2: enabling device (0000 -> 0002) [ 15.815347] igb: probe of 0005:01:00.2 failed with error -2 [ 15.815633] igb 0005:01:00.3: Adding to iommu group 57 [ 15.815756] igb 0005:01:00.3: enabling device (0000 -> 0002) [ 16.556610] igb: probe of 0005:01:00.3 failed with error -2 While the driver fails the I350 remains discoverable on PCIe nvidia@nvidia-desktop:~$ sudo lspci -v ... 0005:01:00.0 Ethernet controller: Intel Corporation I350 Gigabit Connection (rev 01) Flags: fast devsel, IRQ 203, IOMMU group 57 Memory at 2b28000000 (32-bit, non-prefetchable) [size=128K] I/O ports at 200000 [disabled] [size=32] Memory at 2b28080000 (32-bit, non-prefetchable) [size=16K] Capabilities: [40] Power Management version 3 Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+ Capabilities: [70] MSI-X: Enable- Count=10 Masked- Capabilities: [a0] Express Endpoint, MSI 00 Capabilities: [100] Advanced Error Reporting Capabilities: [140] Device Serial Number 02-00-00-ff-ff-aa-bb-cc Capabilities: [150] Alternative Routing-ID Interpretation (ARI) Capabilities: [160] Single Root I/O Virtualization (SR-IOV) Capabilities: [1a0] Transaction Processing Hints Capabilities: [1c0] Latency Tolerance Reporting Capabilities: [1d0] Access Control Services ... What could be causing the igb driver to fail when using the SGMII config? To communicate with the external PHY I want to use the MDIO pass-through, are there any additional steps needed to configure this ? Thank you for any support and insight
XCVR Reset Controller
We are using an Arria 10 device, 10AS057N2F40E2SG, with some JESD204 Receive only channels. The ADC being used is the T.I. ADC09QJ800AAV in JMODE = 2 (for 4 lanes, 8b/10b). I have a XCVR reset controller instantiated in the QSYS design along with the JESD itself plus a few other things - extremely similar to the Intel design example for JESD. On further inspection I found that one of the four rx_is_lockedtodata signals is deactivated, causing the various outputs such as rx_ready to be deactivated, and rx_digitalreset to be activated. The rx_analogreset outputs are remaining low. The particular one of the four rx_is_lockedtodata that is lost seems to be almost random. What could be the cause of this regular event? Thanks David
DisplayPort design: "RX channel * and TX channel * are locked to the same duplex channel." Error
I am using four Displayport interfaces (2 Tx, 2 Rx). When I try to fit the design, I receive this error: "Error(12787): RX channel * and TX channel * are locked to the same duplex channel. In order for both the RX and TX channel to use the same duplex channel, you must assign them to the same group so the Fitter merges them into a single Avalon Memory-Mapped interface. To assign both channels to a group, use the Transceiver Avalon Memory-Mapped Interface Group logic option." for all 16 channels. I have set up the transceivers in the same way as in the design example and included these assignments as suggested by the error message, but the error persists. Note that the design compiles just fine for only 2 interfaces (1 Tx, 1 Rx). This is being built for a 10AS032H3F34E2SG. set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to DP_TX_A_p[0] -entity a10_dp_demo set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to DP_RX_A_p[0] -entity a10_dp_demo set_instance_assignment -name XCVR_RECONFIG_GROUP 2 -to DP_TX_A_p[1] -entity a10_dp_demo set_instance_assignment -name XCVR_RECONFIG_GROUP 2 -to DP_RX_A_p[1] -entity a10_dp_demo set_instance_assignment -name XCVR_RECONFIG_GROUP 3 -to DP_TX_A_p[2] -entity a10_dp_demo set_instance_assignment -name XCVR_RECONFIG_GROUP 3 -to DP_RX_A_p[2] -entity a10_dp_demo set_instance_assignment -name XCVR_RECONFIG_GROUP 4 -to DP_TX_A_p[3] -entity a10_dp_demo set_instance_assignment -name XCVR_RECONFIG_GROUP 4 -to DP_RX_A_p[3] -entity a10_dp_demo set_instance_assignment -name XCVR_RECONFIG_GROUP 5 -to DP_TX_B_p[0] -entity a10_dp_demo set_instance_assignment -name XCVR_RECONFIG_GROUP 5 -to DP_RX_B_p[0] -entity a10_dp_demo set_instance_assignment -name XCVR_RECONFIG_GROUP 6 -to DP_TX_B_p[1] -entity a10_dp_demo set_instance_assignment -name XCVR_RECONFIG_GROUP 6 -to DP_RX_B_p[1] -entity a10_dp_demo set_instance_assignment -name XCVR_RECONFIG_GROUP 7 -to DP_TX_B_p[2] -entity a10_dp_demo set_instance_assignment -name XCVR_RECONFIG_GROUP 7 -to DP_RX_B_p[2] -entity a10_dp_demo set_instance_assignment -name XCVR_RECONFIG_GROUP 8 -to DP_TX_B_p[3] -entity a10_dp_demo set_instance_assignment -name XCVR_RECONFIG_GROUP 8 -to DP_RX_B_p[3] -entity a10_dp_demo
