Nios IDE CPU Detection
Hi, I am trying to create bsp and software for Nios V , using Eclipse IDE. When specifying a new projcet and its .sopc file i see message CPU not detected. And i also see message the NIOS_EDS environment variable not set. See screen shot attached . I verified via command prompt the environment variable is set and can be verified. Also i noticed there are no examples installed at this path : C:\intelFPGA_lite\24.1std\nios2eds Looking forward to resolve these issues, Thanks, Regards,
not able to use multiple niosV cores at the same time
when I run ultiple niosV cores at the same time im not able to acess each of them even though i am able to detect them , i am faced with even though detecting gives me and i am unable to use the cores likewise this is my file on platform designerSysID Timestamp
Hi, I would like to get the timestamp using the System ID Peripheral IP (v 19.1.8) which is connected to NIOS-V IP (26.0.0). I am using Quartus Prime Pro version 25.1.1. Using the NIOS program I am able to correctly access and print the System ID parameter that has been configured, but the returned timestamp seems to be wrong (printing: Tue Feb 4 18:03:27 2003, instead of today's date). Would you please advise if I am making any mistake in accessing the SysID timestamp, and if there is any other configuration that needs to be done on the IP? Following is my code running on the Nios-V processor and the corresponding printout.
Nios V/m JTAG run‑control HALT fails — Debug Module healthy, hart never halts
## Summary On a Nios V/m soft processor, JTAG **halt** never succeeds: the Debug Module enumerates and answers DMI cleanly, the hart runs and is resettable via `ndmreset`, but a `haltreq` is ignored — `dmstatus` stays `0x00400cc3` (`allrunning=1`, `allhalted=0`) indefinitely. `niosv-download`, Intel's OpenOCD build, and the Ashling RiscFree GDB server **all** fail identically with *"Could not halt the target: timeout occurred"* / *"Unable to halt … Hart 0 failed to halt during examine"*. ## Environment - Quartus Prime **Pro 26.1** (Build 110). - Nios V/m IP `intel_niosv_m` (unit `intel_niosv_m_unit_2600`, debug submodule `intel_niosv_dbg_mod_210`). - Device: Arria 10 **`10AX022C4U19E3SG`**. - Programmer: **USB‑BlasterII** (cable index 2). Single device on the chain (`JTAG ID 0x02E220DD`). - CPU clock: IOPLL `outclk0` = **100 MHz**, PLL locked (verified). Design Fmax = 131.6 MHz (timing met). ## Symptom (verbatim) ``` Internal error. Could not halt the target: timeout occurred (Ashling ash-riscv-gdb-server) Error: Unable to halt. dmcontrol=0x10000001, dmstatus=0x00400cc3 Error: Fatal: Hart 0 failed to halt during examine (Intel OpenOCD) ``` ## Direct DMI evidence (via OpenOCD `aji_client`, low‑level `dmi_read`/`dmi_write`) - SLD node enumerates: `jtagconfig -n` → `Node 08986E00 Nios V #0`. - `dmstatus` (running) = `0x00400cc3` → version=3, authenticated, **anyrunning/allrunning=1, allhalted=0**. - `abstractcs` = `0x08000002` → **progbufsize=8, datacount=2, cmderr=0** (DM healthy). - `sbcs` = `0x00000000` → **no System Bus Access** in this DM. - Direct `dmcontrol = 0x80000001` (haltreq + dmactive) → `dmstatus` stays `0x00400cc3` (**allhalted never asserts**). - `ndmreset` **works**: asserting it sets `dmstatus` havereset bits (→ `0x004c0cc3`); the hart resets and resumes. - `hasresethaltreq = 0` (halt‑on‑reset not implemented — separate facility, not the cause). ## Exhaustively ruled out | Hypothesis | Result | |---|---| | CPU clock wrong | Fixed/verified 100 MHz, PLL locked | | Timing closure | Met (Fmax 131.6 MHz) | | JTAG TCK rate | Tried 24 MHz → 6 MHz (`jtagconfig --setparam … JtagClock`) — no change | | Debugger choice | `niosv-download` = Intel OpenOCD = Ashling RiscFree — **identical** failure | | Command timeout | 120 s configured; manual `haltreq` inert | | `Enable Reset from Debug Module` | Enabled + `dbg_reset_out→ndm_reset_in` looped → `ndmreset` works, **halt still fails** | | `instruction_manager → dm_agent` mapping | Added; no effect (and PD won't place it in the instruction map) | | Stale/composed IP generation | **Removed and re‑added a FRESH `intel_niosv_m` (enableDebug=1, enableDebugReset=1), full reconnect + regenerate + recompile → identical failure** | ## Conclusion / request A correctly‑configured, freshly‑generated Nios V/m core does **not** enter Debug Mode on `haltreq` on this device/toolchain, although the Debug Module is fully responsive over DMI and `ndmreset` works. Per the RISC‑V External Debug spec, an *available* running hart must halt within <1 s of `haltreq`; this one never does. The fault appears to be in the **hart‑side debug (Sdext) halt path** of the Nios V/m IP for this version/device, or a board‑level JTAG halt‑path issue. **Questions for Intel/Altera:** - **Q1.** Is there a known erratum for Nios V/m where the DM enumerates/answers DMI but the hart ignores `haltreq` (`allhalted` never asserts)? Fixed in a specific Quartus Pro / Nios V IP version? - **Q2.** Beyond `Enable Debug`, is any parameter/connection required for the hart to honor `haltreq`? - **Q3.** Any documented Arria 10 `10AX022C4U19E3SG` JTAG/SLD interaction with Nios V run‑control halt? Related (please confirm whether either covers this *post‑enumeration* halt timeout): Intel KB **000096654**; community thread **1404335**. (KB **000096246** is a different *detection*-only defect — not this.)
NIOS II "Verify failed" for on-chip memory 128k
Hello! I'm using a Cyclone 10LP FPGA 10CL055YU484I7G FPGA. I have a 11k size program for NIOS II. I have a large on chip RAM (because I have a larger program which I want to use later) of 128k. Everything compiles and links OK. But when I try to download the program I get a "Verify failed between address 0x20000 and 0x2FFFF". The 128K memory is located 0x20000 to 0x3FFFF If I reduce the RAM to 32K, for example, everything works great!!. The initialize memory content option is turned on for the memory The BOOT RAM starts at 0x00000 If I download a bigger program (117k), I still get the same error. Thanks
NIOS-V QSYS Warning Properties (associatedClock) have been set on
Hello, I have a really basic setup of a NIOS V system, but get Warnings in QSYS (using Quartus 25.1 Standard) about Properties of associatedClock: System: Warning: Warning: nios_subsystem.intel_niosv_m_0: Properties (associatedClock) have been set on interface reset - in composed mode these are ignored Warning: nios_subsystem.intel_niosv_m_0: Properties (associatedClock,associatedReset) have been set on interface instruction_manager - in composed mode these are ignored Warning: nios_subsystem.intel_niosv_m_0: Properties (associatedClock,associatedReset) have been set on interface data_manager - in composed mode these are ignored Questions: What is "composed mode" and how can I control it? There is no NIOS Parameter associated with it This appears in a basic setup simply by adding NIOS V to the system. How do I get rid of this warning? best regards Fabian
DE23-Lite + Quartus Pro 25.1 + Nios V/g: no Nios V instance, no JTAG UART
Hi, I’m working on a Terasic DE23-Lite board (Agilex 3 A3CZ135BB18AE7S) using Quartus Prime Pro 25.1, and I’m seeing a runtime debug/service issue that I have not been able to resolve. System details: Board: Terasic DE23-Lite FPGA: Agilex 3 A3CZ135BB18AE7S Quartus Prime Pro: 25.1 CPU in Platform Designer: Nios V/g Project started from the Terasic SDRAM_Test_NiosV / golden_top example USB-Blaster III is detected normally as DE23-Lite [USB-1] What works: quartus_pgm programs the .sof successfully jtagconfig sees the board and FPGA in the JTAG chain Simple RTL-only hardware tests work CLOCK0_50-driven LED blink works KEY0-driven LED test works So basic board programming, raw JTAG visibility, and simple user logic are all working. What does not work: niosv-download fails with: "There are no devices with valid Nios V instance(s)" "ERROR: Failed to generate OpenOCD config file." juart-terminal fails with: "There are no JTAG UARTs available which match the --device and --instance options you provided." In System Console, the following all return nothing: get_service_paths device get_service_paths master get_service_paths processor get_service_paths jtag_debug SignalTap also does not enumerate at runtime and reports that the device needs to be programmed / instance not found, even after compile and program. Important points: The generated Platform Designer system does include Nios V/g debug-related logic and JTAG UART in the generated HDL. The top-level does instantiate the generated nios_system. The QSF includes the Qsys system. The fit report shows SignalTap content present in the fitted image. So this does not look like a missing-instance-in-the-design problem. It looks more like raw JTAG chain works, but no higher-level runtime services enumerate after configuration. One thing I found: In the example golden_top.v, the Nios system clock connection had a typo: .clk_clk(CLOCK1_51)instead of a real clock signal. I corrected that and also tested CLOCK0_50. That did not resolve the no-instance / no-JTAG-UART / no-service-paths issue. Another issue I found and fixed: There was a stale on-chip memory init reference to ram.hex: "Cannot find Memory Initialization File (.mif) or Hexadecimal (Intel-Format) File (.hex) C:/fpga/SDRAM_Test_NiosV/ram.hex -- setting all initial values to 0." I removed that stale reference. It did not fix the runtime service visibility problem. Current question: Has anyone seen a case on DE23-Lite / Agilex 3 / Quartus Pro 25.1 where the JTAG chain is visible and programming succeeds, but Nios V instances, JTAG UART, System Console service paths, and SignalTap all fail to enumerate at runtime? I’m looking for guidance on what layer to check next: JTAG service / SLD runtime visibility Agilex 3 user-mode debug exposure board/project configuration settings Quartus 25.1-specific issue anything DE23-Lite-specific in the Terasic example flow Any suggestions would be appreciated. Thanks, SteveUnable to transmit out of 16550 Compatible UART
Hi I am following the example of the 16550 Compatible UART in the Embedded peripherals IP User Guide and using the provided code I am not seeing any data in the loopback configuration. Software is Quartus Prime Lite 18.1 Any idea or suggestions is greatly appreciated. I'm not sure if I need to configure any registers?
NIOS interface to HPS in Agilex 5 for communication.
The question is about having NIOS design interacting with HPS of same FPGA. The NIOS would be created as design partition and imported to the HPS project. My understanding is normally this is done through the FPGA2HPS/HPS2FPGA bridge. How this is implemented in project where the NIOS is imported design partition in the HPS project.
