DE23-Lite + Quartus Pro 25.1 + Nios V/g: no Nios V instance, no JTAG UART

Hi,

I’m working on a Terasic DE23-Lite board (Agilex 3 A3CZ135BB18AE7S) using Quartus Prime Pro 25.1, and I’m seeing a runtime debug/service issue that I have not been able to resolve.

System details:

• Board: Terasic DE23-Lite
• FPGA: Agilex 3 A3CZ135BB18AE7S
• Quartus Prime Pro: 25.1
• CPU in Platform Designer: Nios V/g
• Project started from the Terasic SDRAM_Test_NiosV / golden_top example
• USB-Blaster III is detected normally as DE23-Lite [USB-1]

What works:

• quartus_pgm programs the .sof successfully
• jtagconfig sees the board and FPGA in the JTAG chain
• Simple RTL-only hardware tests work
• CLOCK0_50-driven LED blink works
• KEY0-driven LED test works

So basic board programming, raw JTAG visibility, and simple user logic are all working.

What does not work:

• niosv-download fails with:
• "There are no devices with valid Nios V instance(s)"
• "ERROR: Failed to generate OpenOCD config file."

juart-terminal fails with:

• "There are no JTAG UARTs available which match the --device and --instance options you provided."

In System Console, the following all return nothing:

• get_service_paths device
• get_service_paths master
• get_service_paths processor
• get_service_paths jtag_debug

SignalTap also does not enumerate at runtime and reports that the device needs to be programmed / instance not found, even after compile and program.

Important points:

• The generated Platform Designer system does include Nios V/g debug-related logic and JTAG UART in the generated HDL.
• The top-level does instantiate the generated nios_system.
• The QSF includes the Qsys system.
• The fit report shows SignalTap content present in the fitted image.

So this does not look like a missing-instance-in-the-design problem. It looks more like raw JTAG chain works, but no higher-level runtime services enumerate after configuration.

One thing I found:

• In the example golden_top.v, the Nios system clock connection had a typo: .clk_clk(CLOCK1_51)instead of a real clock signal.

I corrected that and also tested CLOCK0_50. That did not resolve the no-instance / no-JTAG-UART / no-service-paths issue.

Another issue I found and fixed:

• There was a stale on-chip memory init reference to ram.hex: "Cannot find Memory Initialization File (.mif) or Hexadecimal (Intel-Format) File (.hex) C:/fpga/SDRAM_Test_NiosV/ram.hex -- setting all initial values to 0."

I removed that stale reference. It did not fix the runtime service visibility problem.

Current question: Has anyone seen a case on DE23-Lite / Agilex 3 / Quartus Pro 25.1 where the JTAG chain is visible and programming succeeds, but Nios V instances, JTAG UART, System Console service paths, and SignalTap all fail to enumerate at runtime?

I’m looking for guidance on what layer to check next:

• JTAG service / SLD runtime visibility
• Agilex 3 user-mode debug exposure
• board/project configuration settings
• Quartus 25.1-specific issue
• anything DE23-Lite-specific in the Terasic example flow

Any suggestions would be appreciated.

Thanks,

Steve