Why are there intermittent calibration failures in the External Memory Interfaces Agilex® 5 FPGA E-Series IP?
Description Due to a problem in Quartus® Prime Pro Edition Software version 25.3.1 and earlier, you may run into intermittent EMIF calibration failures on LPDDR4 1CHx32, 2-Rank configurations running at 1333 MHz on Agilex® 5 FPGA E Series devices. Resolution To work around this problem, disable cross-rank delay averaging by enabling the following debug flag in the parameter table: DBG_CFG_DISABLE_RANK_AVG_AND_OVR This prevents the firmware from averaging DQS-WR delays across ranks, which eliminates the invalid delay setting that causes the MGN-stage calibration failure. Note: Disabling rank averaging may affect traffic stability in some configurations. A patch is available to fix this problem in Quartus Prime Pro Edition Software version 25.3.1. Download and install the below 1.04 patch. This problem has been fixed beginning with version 26.1 of the Quartus Prime Pro Edition Software.Why is Agilex® 5 and Agilex® 3 FPGA External Memory Interfaces (EMIF) IP missing from the BSP Linker when the Nios® V processor Board Support Package is generated?
Description Due to a problem in the Quartus ® Prime Pro Edition starting since software version 24.1, the Agilex ® 5 and Agilex ® 3 FPGA EMIF IP is missing from the BSP Linker when generating the Board Support Package. This might occur for Nios ® V processor designs targeting Agilex 5 FPGA or Agilex 3 FPGA, that uses EMIF IP. This is because Agilex 5 and Agilex 3 FPGA EMIF IP are missing the isMemoryDevice agent information. Refer to Nios® V Processor Software Developer Handbook - Memory-Mapped Slave Information (PDF) for information about isMemoryDevice agent information. Refer to External Memory Interfaces (EMIF) IP User Guide Agilex® 5 FPGAs and SoCs (PDF) for information Agilex ® 5 FPGA EMIF IP. Refer to External Memory Interfaces (EMIF) IP User Guide Agilex® 3 FPGAs and SoCs (PDF) for information Agilex ® 3 FPGA EMIF IP. Resolution To work around this problem in the Quartus ® Prime Pro Edition in all the affected software version, apply either one of the following workarounds: Workaround 1: Manually add isMemoryDevice to the EMIF IP (in Platform Designer only) Select the s*_axi4 signal (mainband AXI4 from fabric to controller) that connects to the Nios ® V processor’s instruction/data manager. Right-click, and click Edit Component Instantiation ... Select s*axi4 and edit the Assignments. Enter new Key as embeddedsw.configuration.isMemoryDevice, and Value as 1. Save the new assignment. Generate a new BSP. Workaround 2: Manually define EMIF IP linker memory device Refer to the Nios V Embedded Processor Design Handbook - Defining Address Span Extender Linker Memory Device. The example demonstrates how to manually define Address Span Extender linker memory device. For this problem, apply the same procedure but on the EMIF IP directly. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software. Related Articles LPDDR4 not available in NIOS® V/g linker script - Agilex® 5 FPGA, Quartus® 26.1 Pro Issue with BSP Creation for Nios® V/m Using LPDDR4 on Agilex® 5 FPGA (Quartus® 24.1 & 24.3.1)Why is the FPGA To HPS bridge not functional in a non-HPS EMIF hardware design in Agilex® 5 FPGA device in 25.3.1 release and earlier?
Description Due to an incorrect configuration in the mpfe_config register in the System Manager, performed by the SDM FW, the FPGA-to-HPS transactions will fail to complete on the Agilex® 5 FPGA device in a hardware design that does not instantiate the HPS EMIF IP created with Quartus® Prime 25.3.1 and before. The problem resides in the incorrect value that the SDM FW assigns to the mpfe_config[f2soc_intfcsel] bit when the HPS EMIF is not instantiated. Under this scenario, it is expected that the f2soc_intfcsel field has a value of ‘1', but this is set to '0’ instead. Resolution To workaround this problem, you can set the mpfe_config[f2soc_intfcsel] bit to '1' in the FSBL. The following snippet shows an example of how to do it in U-Boot SPL: #define MPFE_CONFIG_F2SOC_INTFCSEL_BIT 0 void board_init_f(ulong dummy) { : setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_MPFE_CONFIG, BIT(MPFE_CONFIG_F2SOC_INTFCSEL_BIT)); do_bridge_reset(1, RSTMGR_BRGMODRST_FPGA2SOC_MASK ); : } This needs to be done before the FPGA-to-HPS (F2H) bridge is released from reset. This problem will be fixed in a future release. Note: If your non-HPS EMIF design instantiates the Altera ACE5-Lite Cache Coherency Translator (CCT) and, after applying the above workaround, you observe that read transactions in the FPGA-to-HPS (F2H) bridge succeed, but after a write transaction, the system hangs, you may require an additional fix in the ACCT IP that will be released together with the mpfe_config[f2soc_intfcsel] configuration fix. Please refer to Why does the Agilex® 5 FPGA Hard Processor System hang during ACCT IP operations when translating AXI4 to ACE5‑LITE?Why does my single rank DDR5 RDIMM design fail to compile after upgrading to Quartus® Prime Pro Edition Software version 26.1?
Description Starting with Quartus® Prime Pro Edition software version 26.1, the DDR5 DIMM External Memory Interfaces (EMIF) IP explicitly generates two chip select (CS) signals per sub‑channel for DDR5 RDIMMs in the HDL output, even when using single‑rank RDIMMs. This is required because DDR5 RDIMM calibration and RCD operations depend on the presence of both CS signals, regardless of the number of ranks. Enforcing the generation of both CS0 and CS1 ensures that these signals are properly routed from the FPGA to the DIMM connector and prevents cases where CS1 may be left unconnected on the PCB, which could result in initialization or calibration failures. After upgrading to this software version, compilation may fail if the existing top‑level design exposes only one CS pin per sub‑channel. Resolution To resolve this issue, update your top‑level design to expose two CS pins per sub‑channel and connect both signals to the DDR5 DIMM External Memory Interfaces (EMIF) IP in the project. Before: Verilog output wire [0:0] mem_0_cs_n, output wire [0:0] mem_1_cs_n, After: Verilog output wire [1:0] mem_0_cs_n, output wire [1:0] mem_1_cs_n,What is the maximum memory clock frequency for DDR4 in Arria® 10 FPGAs and SoC FPGAs?
Description In Quartus® Prime Pro Edition software version 24.3, users can configure the memory clock frequency to 1333 MHz in the External Memory Interfaces Arria® 10 FPGA IP. However, the External Memory Interfaces Arria 10 FPGA IP User Guide specifies a maximum supported configuration of 1200 MHz. Resolution Users may choose to operate the External Memory Interfaces Arria 10 FPGA IP beyond the published specifications, including overclocking, at their own risk.Why does the example design generation of High Bandwidth Memory (HBM2E) Interface Agilex® 7 FPGA M-Series FPGA IP fail on Window* OS?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, the example design generation of High Bandwidth Memory (HBM2E) Interface Agilex® 7 FPGA M-Series FPGA IP might fail. This problem only occurs on Windows* OS. This problem occurs because the location of quartus_py.exe file has changed but the IP still calls the file from the previous location. Resolution To work around this problem, copy the quartus_py.exe file from <Quartus installation path>\qcore\bin64\quartus_py.exe to <Quartus installation path>\quartus\bin64\quartus_py.exe This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why does the EMIF and Ethernet IP report hold violations in Timing Analyzer?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1.1 and 24.3, you might see hold timing violations in Timing Analyzer when using the EMIF and Ethernet IPs. This problem only refers to Agilex™ 7 FPGA devices. Resolution This problem has been resolved in Quartus® Prime Pro Edition Software version 25.3.Why are there minimum pulse width violations in DDR5 Component External Memory Interfaces (EMIF) IP and DDR5 DIMM External Memory Interfaces (EMIF) IP of Agilex® 7 FPGA M-Series and Agilex® 5 FPGA D-Series devices?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, DDR5 Component External Memory Interfaces (EMIF) IP and DDR5 DIMM External Memory Interfaces (EMIF) IP might show minimum pulse width violations. Resolution It is safe to ignore these minimum pulse width violations. The problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1.Can LPDDR5 External Memory Interfaces (EMIF) IP support single VDD2 rail mode in Agilex™ 5 FPGA and Agilex™ 7 FPGA M‑Series devices?
Description No. LPDDR5 External Memory Interfaces (EMIF) IP in Agilex™ 5 FPGA and Agilex™ 7 FPGA M‑Series devices only supports dual VDD2 rail mode. Resolution You need to separate VDD2 power at memory device as follows. VDD2H = 1.05V VDD2L = 0.9V
