Why does the AXI ready signal assert when EMIF calibration fails in Quartus® Prime Pro Edition 25.1.1?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 25.1.1, the AXI ready signal might assert when EMIF calibration fails for designs targeting Agilex® 5 FPGA E-series devices using the EMIF IP. The AXI ready signal is asserted as expected when calibration passes, but it is also asserted unexpectedly when calibration fails. This behavior can confuse users into thinking the AXI bus is ready to access even though calibration was not successful.

Resolution

This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software.​